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FEATURES

LTC3811 High Speed Dual, Multiphase Step-Down DC/DC Controller DESCRIPTION
The LTC(R)3811 is a dual, PolyPhase(R) synchronous stepdown switching regulator controller optimized for output voltages up to 3.3V. The LTC3811 includes high bandwidth error amplifiers as well as a high speed differential remote sense amplifier. The sense voltage range is programmable from 24mV to 85mV, allowing the use of either the inductor DCR or a discrete sense resistor. Multiphase operation is made possible using the MODE/SYNC input, the CLKOUT output and the PHASEMODE control pin, allowing 1-, 2-, 3-, 4-, 6- or 12-phase operation. Large internal gate drivers minimize switching losses and allow the use of multiple power MOSFETs connected in parallel for high current applications. The operating frequency of the LTC3811 can be programmed from 250kHz to 750kHz and can also be synchronized to an external clock using the internal PLL. Tracking and sequencing are possible with the LTC3811, and soft-start is programmed with an external capacitor. Shutdown reduces supply current to 20A.
, LT LTC, LTM and PolyPhase are registered trademarks of Linear Technology , Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6304066, 5929620, 6177787, 6144194, 6580258, 5705919.

Fixed Frequency, Peak Current Mode Control 0.5% Output Accuracy Over Temperature Optimized for Low VOUT Applications (Up to 3.3V) Dual or Single Output, Multiphase Operation Wide VIN Range: 4.5V to 30V Operation High Speed Differential Remote Sense Amplifier Inductor DCR or Sense Resistor Capable Adjustable Peak Current Sense Voltage: 24mV to 85mV Very Low Duty Cycle Operation: tON(MIN) = 65ns (Typ) Powerful Internal Gate Drivers Output Voltage Soft-Start, Tracking and Sequencing Programmable Load Line for Reduced COUT Clock Input and Output for Up to 12-Phase Operation Fixed Frequency Operation from 250kHz to 750kHz PLL Synchronization from 150kHz Up to 900kHz Selectable CCM or DCM Operation Available in 5mm x 7mm QFN and G36 Packages
APPLICATIONS

Network Servers High Current ASIC Supplies Low Voltage Power Distribution
TYPICAL APPLICATION
Dual Output, 2-Phase Tracking Core and I/O Supply
VIN 4.5V TO 14V VIN TG1 BOOST1 SW1 BG1 RUN1 RUN2 SENSE1+ SENSE1- RNG1 VOUT1 2V 15A RNG2 FB1 LTC3811 SENSE2+ SENSE2- DIFF/IN+ DIFF/IN- DIFF/OUT FB2 INTVCC DRVCC TG2 BOOST2 SW2 BG2 PGND
Load Step
VOUT 100mV/DIV
IL 5A/DIV
COMP1 COMP2 SS/TRACK1 SGND SS/TRACK2
VOUT2 1.5V 15A
VIN = 12V VOUT = 2V IOUT = 0A to 12.5A
20s/DIV
3811 TA01b
3811 TA01a
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LTC3811 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN) ......................... -0.3V to 30V Topside Driver Voltages (BOOST1, BOOST2) ............................... -0.3V to 37V Switch Voltage (SW1, SW2) ......................... -5V to 30V BOOST1 - SW1, BOOST2 - SW2 ................. -0.3V to 7V DRVCC, INTVCC, EXTVCC, RUN1, RUN2, DIFF/IN+, DIFF/IN-, PHASEMODE, PGOOD1, PGOOD2, MODE/SYNC Voltages .................................. -0.3V to 7V
FB1, FB2, RNG1, RNG2, SS/TRACK1, SS/TRACK2, PLL/LPF SENSE1+, SENSE1-, SENSE2+, , SENSE2- Voltages................................. -0.3V to INTVCC DRVCC LDO RMS Output Current .........................100mA OperatingTemperature Range (Note 2)..... -40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range................... -65C to 125C Lead Temperature (Soldering, 10 sec) SSOP Package .................................................. 300C
PIN CONFIGURATION
MODE/SYNC TOP VIEW PGOOD1 PGOOD2 PLL/LPF TOP VIEW CLKOUT PGOOD1 RUN1 RUN2 31 BOOST1 30 TG1 29 SW1 28 BG1 27 EXTVCC 39 26 PGND 25 DRVCC 24 VIN 23 BG2 22 SW2 21 TG2 20 BOOST2 13 14 15 16 17 18 19 DIFF/OUT CSOUT PHASEMODE RNG1 DIFF/IN- DIFF/IN+ RNG2 SENSE1+ SENSE1- SS/TRACK1 COMP1 FB1 SGND 1 2 3 4 5 6 7 8 9 36 PGOOD2 35 PLL/LPF 34 MODE/SYNC 33 BOOST1 32 TG1 31 SW1 30 BG1 29 EXTVCC 28 PGND 27 DRVCC 26 VIN 25 BG2 24 SW2 23 TG2 22 BOOST2 21 CLKOUT 20 RNG2 19 RNG1 RUN2 SENSE1+ 1 SENSE1- 2 SS/TRACK1 3 COMP1 4 FB1 5 SGND 6 INTVCC 7 FB2 8 COMP2 9 SS/TRACK2 10 SENSE2 11 SENSE2 12
+ -
38 37 36 35 34 33 32
RUN1
INTVCC 10 FB2 11 COMP2 12 SS/TRACK2 13 SENSE2- 14 SENSE2+ 15 DIFF/OUT 16 DIFF/IN- 17 DIFF/IN+ 18
UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN
TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
G PACKAGE 36-LEAD PLASTIC SSOP WIDE
TJMAX = 125C, JA = 100C/W
ORDER INFORMATION
LEAD FREE FINISH LTC3811EUHF#PBF LTC3811EG#PBF TAPE AND REEL LTC3811EUHF#TRPBF LTC3811EG#TRPBF PART MARKING 3811 LTC3811EG PACKAGE DESCRIPTION 38-Lead (5mm x 7mm) Plastic QFN 36-Lead Plastic SSOP Wide TEMPERATURE RANGE -40C to 85C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC3811 ELECTRICAL CHARACTERISTICS
SYMBOL Input Supply VIN IQ Operating Input Voltage Range Total Quiescent Supply Current Continuous Mode (Note 4) Shutdown Mode RUN Pin Input Leakage Low Level RUN Input Threshold High Level RUN Input Threshold Feedback Voltage Accuracy Feedback Pin Input Current Line Regulation Load Regulation Error Amplifier Unity Gain Crossover Frequency Error Amplifier Maximum Output Voltage (Internally Clamped) FB Voltage Threshold to Disable Error Amplifier Output SS/TRACK1, SS/TRACK2 Charging Currents SS/TRACK1, SS/TRACK2 Pull-Down Resistance in Shutdown Differential Mode Gain, VDIFF/OUT/VDIFF/IN Output Offset Voltage, VDIFF/OUT - VDIFF/IN+ Input Resistance Power Supply Rejection Ratio Maximum Differential Mode Input Voltage Maximum Sink Current Maximum Source Current Unity Gain Bandwidth Maximum Current Sense Threshold (VSENSE+ - VSENSE-) (Note 6) VFB = 0.575V, VCM = 1.25V VRNG = 0V VRNG = INTVCC VRNG = 2V VFB = 0.625V, VCM = 1.25V VRNG = 0V VRNG = INTVCC VRNG = 2V 8 (Note 5)
The denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VIN = 12V, MODE/SYNC = 0V, unless otherwise specified.
PARAMETER CONDITIONS MIN 4.5 VFB1,2 = 0.7V VRUN1,2 = 0V VRUN1,2 = 3.3V

TYP
MAX 30
UNITS V mA A A V V
10.5 20 -1 1.8 598 597 -100 600
20 40 1 0.3
RUN Pin ON/OFF Control IRUN VIL(RUN) VIH(RUN) VFB1, VFB2 IFB1, IFB2 VFB/VIN VFB/VCOMP f0dB(EA) VOH(EA) VOL(EA) VFB(OFF) Soft-Start/Tracking ISS1, ISS2 RSS1, RSS2 VSS/TRACK1 = VSS/TRACK2 = 0.3V VRUN1 = VRUN2 = 0V -2.5 1 A k
Error Amplifier Characteristics (Both Channels) 602 603 100 0.002 -0.1 -0.01 8 2.6 10 0.3 0.02 mV mV nA %/V % MHz V mV V
VCOMP = 1.25V (Note 5) 4.5V VIN 30V (Note 5) VCOMP = 1.25V to 1.5V (Note 5) (Note 6) VFB = 0.54V, No Load

Error Amplifier Minimum Output Voltage VFB = 0.66V, No Load VINTVCC - VFB
Differential Amplifier AV VOS(DIFF) RIN PSRRDIFF VDM(DIFF) IMAX+ IMAX- f0dB(DIFF) Current Comparators VSENSE(MAX) 14 32.5 60 24 50 85 -21 -41 -67 34 67.5 110 mV mV mV mV mV mV
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VDIFF/IN = 1V to 3.5V, IDIFF/OUT = -100A VDIFF/IN+ = 1.25V, VDIFF/IN- = 0V, IDIFF/OUT = -100A Measured at VDIFF/IN+ 7V VIN 30V VDIFF/IN+ - VDIFF/IN-, Measured at VDIFF/OUT, IDIFF/OUT = -100A
0.995 -6
1.000
1.005 6
V/V mV k dB
160 100 5.5 2 -2
V mA mA MHz
VSENSE(MIN)
Minimum Current Sense Threshold (VSENSE+ - VSENSE-)
3
LTC3811 ELECTRICAL CHARACTERISTICS
SYMBOL ISENSE VCM(CS) PARAMETER Total Sense Pin Current (VSENSE+ + VSENSE-) VSENSE+, VSENSE- Pin Common Mode Input Voltage Range Voltage Position Transconductance, ICSOUT/VSENSE (Note 8) Output Offset Current, Measured at CSOUT Nominal Frequency Lowest Frequency Highest Frequency Minimum Synchronizable Frequency Maximum Synchronizable Frequency Phase Detector Output Current Sinking Sourcing Channel 1 to Channel 2 Phase Relationship (Note 9) Channel 1 to CLKOUT Phase Relationship (Note 9) Low Level CLKOUT Output Voltage High Level CLKOUT Output Voltage MODE/SYNC Input Resistance Low Level MODE/SYNC Input Threshold High Level MODE/SYNC Input Threshold PGOOD Voltage Low PGOOD Leakage Current VFB, PGOOD Overvoltage Threshold VFB, PGOOD Undervoltage Threshold VFB, PGOOD Comparator Hysteresis Delay from UV/OV Condition to PGOOD Falling Delay from UV/OV Fault Recovery to PGOOD Rising Thermal Shutdown Junction Temperature Thermal Shutdown Junction Temperature Hysteresis (Note 6) (Note 6) IPGOOD = 2mA VPGOOD = 6V VFB(OV) - VFB(NOM) in Percent VFB(UV) - VFB(NOM) in Percent UV or OV Comparator 7 -13 10 -10 12 145 38 1.8 0.12 0.30 1.0 13 -7 VSENSE1+ - VSENSE1- = VSENSE2+ - VSENSE2- = 50mV, VCM = 1.25V, VCSOUT = 1.25V VSENSE1+ - VSENSE1- = VSENSE2+ - VSENSE2- = 1.25V, VCSOUT = 1.25V VPLL/LPF Pin Floating, MODE/SYNC = DC Voltage VPLL/LPF = 0V, MODE/SYNC = DC Voltage VPLL/LPF = INTVCC, MODE/SYNC = DC Voltage MODE/SYNC = External Clock MODE/SYNC = External Clock fMODE/SYNC < fOSC fMODE/SYNC > fOSC VPHASMODE = 0V VPHASMODE = 50% INTVCC VPHASMODE = INTVCC VPHASMODE = 0V VPHASMODE = 50% INTVCC VPHASMODE = INTVCC RCLK = 50k to Ground RCLK = 50k to Ground 4.0 5.8 75 0.3 900 -40
The denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VIN = 12V, MODE/SYNC = 0V, unless otherwise specified.
CONDITIONS VCM = 1.25V 0 MIN TYP -1.5 3.5 MAX UNITS A V
Voltage Position Amplifier (QFN Package Only) gm 5.0 mS
IOS(VP)
40
A
Multiphase Oscillator and Phase-Lock Loop (Note 9) fNOM fLOW fHIGH fSYNC(MIN) fSYNC(MAX) IPLL/LPF 450 200 650 500 250 750 125 1000 -4.3 5.1 180 180 120 90 60 240 0.2 550 300 850 175 kHz kHz kHz kHz kHz A A deg deg deg deg deg deg V V k V V V A % % mV s s
1 - 2
1 - CLKOUT
VOL(CLKOUT) VOH(CLKOUT) RMODE/SYNC VIL(MODE/SYNC) VIH(MODE/SYNC) VOL(PGOOD) IPGOOD(OFF) VFB(OV) VFB(UV) VFB(HYST) tPG(FAULT) tPG(OK) Thermal Protection TJSD TJSD(HYST)
Power Good Indicators
165 25
C C
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LTC3811 ELECTRICAL CHARACTERISTICS
SYMBOL VDRVCC VDRVCC(LOAD) VDRVCC(LINE) VDRVCC(UVLO) VDRVCC(HYST) VEXTVCC VEXTVCC(HYST) VEXTVCC(DROP) Gate Drivers tr (TG1, TG2) tf (TG1, TG2) tr (BG1, BG2) tf (BG1, BG2) RDS(ON)(TG) TG1, TG2 RDS(ON)(BG) BG1, BG2 IPK(TG) TG1, TG2 IPK(BG) BG1, BG2 tDEAD1 tDEAD2 tON(MIN) Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Top Gate Pull-Down NMOS On-Resistance Bottom Gate Pull-Down NMOS On-Resistance Top Gate (TG) Peak Source Current Bottom Gate (BG) Peak Source Current Bottom Gate Off to Top Gate On Deadtime Top Gate Off to Bottom Gate On Deadtime Minimum On-Time (Note 6) (Note 6) VCOMP = 1.25V (Note 6, 7) CL = 3300pF (Note 6) CL = 3300pF (Note 6) CL = 3300pF (Note 6) CL = 3300pF (Note 6) TG to SW BG to PGND 20 10 20 10 0.9 0.9 1.0 1.0 30 30 65 ns ns ns ns A A ns ns ns PARAMETER LDO Regulator Output Voltage DRVCC Load Regulation DRVCC Line Regulation LDO Regulator Undervoltage Threshold LDO Regulator Undervoltage Hysteresis EXTVCC Switchover Voltage EXTVCC Switchover Hysteresis EXTVCC Voltage Drop IDRVCC = 20mA, EXTVCC Rising IDRVCC = 20mA IDRVCC = 20mA, VEXTVCC = 5V DRVCC Linear Regulator VEXTVCC = 0V ILOAD = 0mA to 50mA VIN = 8.5V to 30V DRVCC Rising
The denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VIN = 12V, MODE/SYNC = 0V, unless otherwise specified.
CONDITIONS MIN 5.6 -2.0 TYP 6.0 -0.5 0.01 3.7 0.56 4.5 400 100 0.2 MAX 6.4 UNITS V % %/V V V V mV mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Unless otherwise specified, all voltages are relative to SGND and all currents are positive into a pin. Note 2: The LTC3811E is guaranteed to meet performance specifications from 0C to 85C temperature. Specifications over the -40C to 85C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * TBDC/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG * fOSC). See Applications Information for more information. Note 5: The error amplifiers are measured in a feedback loop using an external servo operational amplifier that drives the VFB pin and regulates VCOMP to be equal to the external control voltage.
Note 6: Guaranteed by design, not subject to test. Note 7: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of 50% of IMAX. See Applications Information for more details. Note 8: The voltage positioning amplifier operates as a transconductance amplifier, where the input voltages are the SENSE+ to SENSE- potentials for both channels. The amplifier output current flows through an external resistor in order to program the amount of voltage droop at full load. Note 9: The PHASEMODE function is only available in the QFN package. The 36-lead GW package has a fixed channel 1-to-channel 2 phase relationship of 180C and a channel 1-to-CLKOUT phase relationship of 90C. The version in the 36-lead GW package is therefore optimized for 2- and 4-phase operation. Note 10: Rise and fall times are measured at 10% and 90% levels.
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LTC3811 TYPICAL PERFORMANCE CHARACTERISTICS
Load Step (Pulse Skip Mode)
VOUT 50mV/DIV AC COUPLED VOUT 50mV/DIV AC COUPLED
Load Step (Forced Continuous)
VOUT 50mV/DIV AC COUPLED
Load Step (Forced Continuous with Voltage Positioning)
IL 5A/DIV
IL 5A/DIV
IL1 5A/DIV IL2 5A/DIV
VIN = 12V 20s/DIV VOUT = 1.5V ILOAD = 0.5A TO 8A
3811 G01
20s/DIV VIN = 12V VOUT = 1.5V ILOAD = 0.5A TO 8A
3811 G02
VIN = 12V 50s/DIV VOUT = 1.5V (2-PHASE) ILOAD = 0A TO 15A
3811 G03
Low Duty Cycle Waveforms
Light Load Waveforms (Forced Continuous Mode)
Light Load Waveforms (Pulse Skip Mode)
SW 10V/DIV
SW 5V/DIV VOUT 20mV/DIV AC COUPLED IL 5A/DIV VIN = 20V VOUT = 1.2V ILOAD = 1.5A 250ns/DIV
3811 G04
SW 5V/DIV VOUT 20mV/DIV AC COUPLED IL 5A/DIV VIN = 12V VOUT = 1.5V ILOAD = 300mA 1s/DIV
3811 G05
IL 2A/DIV
VIN = 12V VOUT = 1.5V ILOAD = 300mA
1s/DIV
3811 G06
Efficiency vs Load Current with RSENSE = 1.5m
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 1 10 LOAD CURRENT (A) 100
3811 G07
Efficiency vs Load Current with DCR Sensing
100 95 90 EFFICIENCY (%) 85 80 75 70 VIN = 12V VOUT = 2V
Short-Circut Waveforms
VIN = 12V VOUT = 2V
IL 5A/DIV PGOOD 5V/DIV VOUT 1V/DIV
DISCONTINUOUS FORCED CONTINUOUS
65 60 1
DISCONTINUOUS FORCED CONTINUOUS 10 LOAD CURRENT (A) 100
3811 G08
VIN = 12V VOUT = 1.5V
200s/DIV
3811 G09
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LTC3811 TYPICAL PERFORMANCE CHARACTERISTICS
FB Voltage vs Temperature
0.6030 0.6025 0.6020 0.6015 FB VOLTAGE (mV) FB VOLTAGE (mV) 0.6010 0.6005 0.6000 0.5995 0.5990 0.5985 0.5980 0.5975 0.5970 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G10
FB Voltage Line Regulation
600.5 DIFFERENTIAL AMPLIFIER GAIN (V/V) 600.4 600.3 600.2 600.1 600.0 599.9 599.8 599.7 599.6 599.5 0 4 8 12 16 20 24 28 SUPPLY VOLTAGE (V) 32 36 1.010 1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992
Differential Amplifier Gain vs Temperature
0.990 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G12
3811 G11
Oscillator Frequency vs Temperature
800 700 600 FREQUENCY (kHz) VPLL/LPF = FLOATING 500 400 300 200 100 0 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (C)
3811 G13
Oscillator Frequency vs Supply Voltage
SHUTDOWN MODE SUPPLY CURRENT (A) 800 40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V) 35 40 700 OSCILLATOR FREQUECY (kHz) 600 VPLL/LPF = FLOATING 500 400 300 200 100 0 VPLL/LPF = 0V VPLL/LPF = INTVCC
Shutdown Mode Supply Current vs Supply Voltage
85C 25C -40C
VPLL/LPF = INTVCC
VPLL/LPF = 0V
0
4
8
12 16 20 24 28 SUPPLY VOLTAGE (V)
32
36
3811 G14
3811 G15
Supply Current vs Supply Voltage
15 14 SS/TRACK PIN CURRENT (A) 13 SUPPLY CURRENT (mA) 12 11 10 9 8 7 6 5 0 4 8 12 16 20 24 28 SUPPLY VOLTAGE (V) 32 36 -40C 25C 85C 3.0 2.9
SS/TRACK Pin Current vs Common Mode Voltage
3.0 2.9 SS/TRACK PIN CURRENT (A) 0 100 200 300 400 500 600 COMMON MODE VOLTAGE (mV) 700
3811 G17
SS/TRACK Pin Current vs Temperature
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G18
3811 G16
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LTC3811 TYPICAL PERFORMANCE CHARACTERISTICS
DRVCC Line Regulation
6.010 6.008 6.006 DRVCC VOLTAGE (V) DRVCC VOLTAGE (V) 6.004 6.002 6.000 5.998 5.996 5.994 5.992 5.990 0 4 8 12 16 20 24 28 SUPPLY VOLTAGE (V) 32 36 5.5 5.4 0 50 100 150 200 250 300 DRVCC LOAD CURRENT (mA) 350 6.0 5.9 5.8 5.7 5.6 DRVCC (V) 6.1
DRVCC Load Regulation
6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6
DRVCC vs Temperature
5.5 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G21
3811 G19
3811 G20
DRVCC Undervoltage Lockout Thresholds vs Temperature
UNDERVOLTAGE LOCKOUT THRESHOLDS (V) 5.0 4.5 DROPOUT VOLTAGE (mV) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G22
LDO Dropout Voltage vs Current
700 600 EXTVCC THRESHOLDS (V) TA = 25C 5.0
EXTVCC Thresholds vs Temperature
DRVCC RISING
EXTVCC RISING 4.5
500 400 300 200 100 0 0 10 20 30
DRVCC FALLING
4.0
EXTVCC FALLING
3.5
40 50 60 70 80 90 100 CURRENT (mA)
3811 G23
3.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G24
EXTVCC Switch IR Drop vs Current
500 450 EXTVCC SWITCH IR DROP (mV) 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 EXTVCC CURRENT (mA)
3811 G25
RUN Pin Threshold vs Supply Voltage
2.5 CURRENT SENSE AMP gm (mS) 32 36
3811 G26
Current Sense Amplifier gm vs Temperature
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5
TA = 25C
RUN PIN THRESHOLD (V)
2.0
1.5
25C
-40C
1.0
85C
0.5
0 0 4 8
12 16 20 24 28 SUPPLY VOLTAGE (V)
3.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G27
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LTC3811 TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold vs COMP Pin Voltage
100 CURRENT SENSE THRESHOLD (mV) 80 60 40 20 0 -20 -40 -60 -80 0 0.5 1 1.5 2 COMP PIN VOLTAGE (V) 2.5 3
3811 G28
Maximum SENSE Pin Voltage vs Temperature
MAXIMUM SENSE PIN VOLTAGE (mV) 90 80 70 60 50 40 30 20 10 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G29
Maximum Current Sense Threshold vs VRNG Voltage
MAXIMUM CURRENT SENSE THRESHOLD (mV) 90 80 70 60 50 40 30 20 10 0 0.5 0.7 0.9 1.1 1.3 1.5 VRNG VOLTAGE (V) 1.7 1.9
3811 G30
100 RNG = 2V RNG = INTVCC RNG = 0V
RNG = 2V
RNG = INTVCC
RNG = 0V
Foldback Current Limit
60 MAXIMUM SENSE THRESHOLD (mV) 55 50 45 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 FB VOLTAGE (mV) 600 700 RNG = INTVCC MAXIMUM SENSE PIN THRESHOLD (mV) 60 50 40 30 20 10 0
Maximum SENSE Pin Threshold vs Duty Cycle
2.5
SENSE Pin Current vs Common Mode Voltage
SENSE PIN CURRENT (A) 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%)
3811 G32
2.0 1.5
1.0
0.5
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMMON MODE VOLTAGE (V)
3811 G33
3811 G31
SENSE Pin Current vs Temperature
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3811 G34
Maximum SENSE Pin Threshold vs Common Mode Voltage
55 MAXIMUM SENSE PIN THRESHOLD (mV) 54 53 FREQUENCY (kHz) 52 51 50 49 48 47 46 45 0 0.5 1.5 2 1 2.5 3 3.5 COMMON MODE VOLTAGE (V) 4 RNG = INTVCC 1200 1100 1000 900 800 700 600 500 400 300 200 100 0
Frequency vs PLL/LPF Pin Voltage
SENSE PIN CURRENT (A)
0
0.5 1.5 2 1 PLL/LPF PIN VOLTAGE (V)
2.5
3811 G36
3811 G35
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LTC3811 TYPICAL PERFORMANCE CHARACTERISTICS
Top Gate Turn-On Waveform Driving Renesas RJK0305DPB Top Gate Turn-Off Waveform Driving Renesas RJK0305DPB Bottom Gate Turn-On Waveform Driving Renesas RJK0301DPB
TG - SW
TG - SW 2V/DIV 2V/DIV
2V/DIV
VIN = 12V VOUT = 1.5V IOUT = 5A
10ns/DIV
3811 G37
VIN = 12V VOUT = 1.5V IOUT = 5A
10ns/DIV
3811 G38
VIN = 12V VOUT = 1.5V IOUT = 5A
25ns/DIV
3811 G39
Bottom Gate Turn-Off Waveform Driving Renesas RJK0301DPB
IL 5A/DIV
Single Output, 2-Phase Current Sharing Waveforms
Start-Up Into a Pre-Biased Output Capacitor
1V/DIV 1V PRE BIAS OV
2V/DIV
SW1 10V/DIV SW2 10V/DIV VIN = 12V VOUT = 1.5V IOUT = 5A 25ns/DIV
3811 G40
VIN = 12V VOUT = 1.5V IOUT = 16A
1s/DIV
3811 G41
VOUT = 3.3V
500s/DIV
3811 G42
Sequenced Start-Up
RUN1 2V/DIV RUN2 5V/DIV VOUT1 = 2V VOUT2 = 1.5V 500mV/DIV VIN = 12V 10ms/DIV RLOAD1 = RLOAD2 = 1.5 RUN2 CONNECTED TO PGOOD1
3811 G43
Ratiometric Tracking Start-Up
Coincident Tracking Start-Up
VOUT1 = 2V VOUT2 = 1.5V 500mV/DIV 500mV/DIV
VIN = 12V 5ms/DIV RLOAD1 = RLOAD2 = 1.5
3811 G44
5ms/DIV
3811 G45
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10
LTC3811 PIN FUNCTIONS
BG1, BG2: High Current Gate Driver Outputs for the N-Channel Lower Power MOSFETs. BOOST1, BOOST2: Bootstrapped Supply Inputs to the Topside Floating Drivers. A low ESR (X5R or better) ceramic bypass capacitor should be connected between the BOOST pin and the SW pin as close as possible to the IC. CLKOUT: A Digital Output Used for Daisy-Chaining Multiple LTC3811 ICs in Multiphase Systems. The PHASEMODE pin voltage controls the phase relationship between the channel 1 TG signal and CLKOUT. COMP1, COMP2: Error Amplifier Output Voltages. The error amplifiers in the LTC3811 are high bandwidth, low offset true operational amplifiers that have low output impedance. As a result, the outputs of two active error amplifiers cannot be directly connected together! For multiphase operation, connecting the FB pin of a slave error amplifier to INTVCC will disable the output of that amplifier. Multiphase operation can then be achieved by connecting all of the COMP pins together and using one channel as the master and all of the others as slaves. The FB and COMP pins are also used for compensating the control loop of the converter. CSOUT (QFN Only): Output of the Voltage Positioning gm Amplifier. This pin allows the user to program the amount of voltage droop in the output voltage at high load current. The output of the voltage positioning gm amplifier is a bi-directional current proportional to the (SENSE+ - SENSE-) voltages for both channels. The gm is internally fixed to 5mS. Forcing the gm amplifier output current through a low value external resistor will program the amount of voltage droop seen at the output. See Applications Information for more details regarding voltage positioning. DIFF/IN+: Remote Sense Differential Amplifier Positive Input. A low offset, high bandwidth operational amplifier is configured with four precision 80k resistors for a noninverting gain of one. This pin is normally connected to the positive terminal of the decoupling capacitor at the load. DIFF/IN-: Remote Sense Differential Amplifier Negative Input. This pin is normally connected to the negative terminal of the decoupling capacitor at the remote load. The DIFF/IN+ and DIFF/IN- PCB traces should be routed as close as possible and parallel to each other from the IC to the output capacitor. DIFF/OUT: Remote Sense Differential Amplifier Output Voltage, Configured for a Noninverting Gain of One. The voltage at the DIFF/OUT pin is normally connected through an external resistor divider to the FB pin of one channel. The bottom of the divider should be connected to the SGND pin of the IC. DRVCC: Output of the Internal 6V Low Dropout Regulator (LDO), Supply Pin for the Bottom Gate Drivers and Output of the PMOS EXTVCC Switch. A low ESR (X5R or better) 4.7F ceramic bypass capacitor should be connected between the DRVCC pin and the PGND pin, as close as possible to the IC. Exposed Pad (QFN Only): The Exposed Pad of the QFN Leadframe is PGND. EXTVCC: External Power Supply Input to an Internal PMOS Power Switch Connected Between EXTVCC (Drain) and DRVCC (Source). This pin allows an external supply to be used for the high current gate drivers, thereby reducing power dissipation in the LDO and increasing efficiency. When EXTVCC exceeds 4.5V (rising), the high current PMOS switch turns on and shorts EXTVCC to DRVCC, bypassing the internal LDO. See Applications Information for more details.
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11
LTC3811 PIN FUNCTIONS
FB1, FB2: Error Amplifier Feedback Input Pins. The error amplifiers in the LTC3811 are high bandwidth, low offset true operational amplifiers. If differential remote sensing is not used, the FB pin should be connected to a resistor divider from the output of the power supply to SGND with the resistors placed close to the IC. In normal regulation the voltage at the FB pin is 0.6V. If remote sensing is used the FB pin should be connected to a resistor divider from the output of the differential amplifier to SGND. For multiphase operation, connecting the FB pin of a slave error amplifier to INTVCC will disable the output of that amplifier, allowing amplifier outputs to be connected in parallel. INTVCC: Supply Pin for All of the Internal Low Voltage Analog and Digital Control Circuitry, Electrically Isolated from the DRVCC Pin. The INTVCC supply is normally derived by connecting a low value resistor (1) from the output of the LDO (DRVCC) to INTVCC and connecting a 0.1F low ESR (X5R or better) ceramic bypass capacitor connected from INTVCC to SGND. This RC decoupling configuration prevents gate driver switching noise from coupling into the analog control circuitry. The INTVCC decoupling capacitor should be connected as close as possible to the IC pins. MODE/SYNC: Mode Control and PLL Synchronization Input. This pin programs the operating mode and serves as the sync input to the internal phase-lock loop (PLL). Connecting this pin to INTVCC forces continuous operation (regardless of the load current) and connecting it to SGND allows discontinuous mode operation at light load. Applying an external clock between 175kHz and 900kHz will cause the operating frequency to synchronize to the clock. PGND: Power Supply Return Path for the Bottom Side Gate Drivers, Connected to the Sources of the Lower Power MOSFETs. PGND should also be connected to the negative terminal of the DRVCC decoupling capacitor as close as possible to the IC. PGND is electrically isolated from the SGND pin. The Exposed Pad on the bottom of the QFN package is PGND. PGOOD1, PGOOD2: An Open-Drain NMOS Power Good Output. This output turns on, pulling down the PGOOD pin, when the FB voltage falls out of a 10% regulation window. The PGOOD monitor circuit contains a 130s nuisance filter to prevent short duration UV and OV transients from triggering the PGOOD output on, and a 30s filter for the recovery from a fault condition. PHASEMODE (QFN Only): The PHASEMODE pin voltage programs the phase relationship between the channel 1 and channel 2 rising TG signals, as well as the phase relationship between the channel 1 TG signal and CLKOUT. PLL/LPF: Frequency Set and PLL Lowpass Filter Input. When not synchronized, this pin can be used to program the operating frequency. Connecting this pin to SGND forces 250kHz operation and connecting it to INTVCC forces 750kHz operation. Connecting the PLL/LPF pin to a voltage between 0.4V and 2V forces 500kHz operation. When synchronizing to an external clock, this pin serves as the lowpass filter input for the PLL. A series resistor and capacitor connected from PLL/PLF to SGND compensate the PLL feedback loop. RNG1, RNG2: The voltage at this pin programs the sense voltage range for peak current mode control. Connecting this pin to SGND programs a peak sense voltage of 24mV and connecting it to INTVCC programs a peak sense voltage of 50mV. Alternatively, the sense voltage range can be linearly programmed by programming the RNG pin from 0.6V to 2V with a divider from INTVCC to SGND. RUN1, RUN2: On/Off Input Pin for Each Controller. SENSE1+, SENSE2+: Positive Inputs to the Current Comparators and Voltage Positioning gm Amplifier. The COMP pin voltage programs the current comparator offset in order to set the peak current trip threshold. The LTC3811 is capable of sensing current using a discrete resistor in series with the inductor, or by indirectly sensing the voltage drop across the DCR of the inductor. See Applications Information for more details.
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12
LTC3811 PIN FUNCTIONS
SENSE1-, SENSE2-: Negative Inputs to the Current Comparators and Voltage Positioning gm Amplifier. The common mode input voltage range for the current comparators is 0V to 3.5V. SW1, SW2: Bootstrapped Supply Return Paths for the Topside Gate Drivers, Connected to the Sources of the Upper Power MOSFETs. SGND: Signal Ground Pin for the IC. Common to both controllers, this pin should be connected to the negative terminals of the VOUT and INTVCC decoupling capacitors and should be routed separately from any high current paths on the PC board. SS/TRACK1, SS/TRACK2: Combined Soft-Start and Tracking Inputs. For soft-start operation, connecting a capacitor from this pin to ground will control the voltage ramp at the output of the power supply. An internal 2.5A current source will charge the capacitor and thereby control an extra input on the reference side of the error amplifier. For tracking operation, this input allows the start-up of a secondary output to track a primary output according to a ratio established by a resistor divider from the primary output to the secondary error amplifier track pin. For coincident tracking of both outputs at start-up, a resistor divider with values equal to those connected to the secondary FB pin from the secondary output should be used to connect the secondary track input from the primary output. TG1, TG2: High Current Gate Driver Outputs for the N-Channel Upper Power MOSFETs. VIN: Main Supply Input. A low ESR ceramic bypass capacitor should be connected between this pin and SGND.
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13
MODE/SYNC 1V FC DRVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB VIN
RLP CLK1 VCO CLK2 TOP CIN SW S VFB R SHDN 0.54V UVLO PGND FC 1.1V OT 200k RUN COUT 5.4V SENSE+ SENSE- L RSENSE VOUT BOT BG Q DRVCC TOP ON SWITCH LOGIC Q BOT OV 0.66V DROP OUT DET TG CB
LTC3811
PLL/LPF MODE/SYNC
CLP
CLKOUT
FUNCTIONAL DIAGRAM
OV2 UV
PGOOD1
PGOOD UV2 LOGIC AND OV1 FILTER UV1
CSAMP
CSOUT SGND
+ gm - +
SENSE1+ SENSE2+ SENSE2- SENSE1-
+ - -
RAVP (OPTIONAL)
DIFFIN+
80k
80k
DIFFIN- DIFFAMP SLOPE COMP
80k
+ -
VFB
DIFFOUT
80k
VIN
VIN
EN
+ -
6V LDO ISET
DRVCC
FOLDBACK
+ - - + - +
INTVCC
0.3V VFB
INTVCC
+ -
UVLO
3.7V VIN
SGND
+ -
BIAS OT
REF
OVER TEMP
+
-
+ -
EXTVCC
4.5V
+ -
X
V-TO-I
EA
SS/TRACK 0.600V CC2
-
SHDN RNG
+ -
+ -
+ -
PGOOD2
+ -
PHASEMODE
+ -
ICMP IR VFB R2 RC R1
14
+
INTVCC COMP CC INTVCC 2.5A SS/TRACK CSS INTVCC
3811 FD
fCLK
PHASE DET
60k
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LTC3811 OPERATION
Main Control Loop The LTC3811 uses a constant frequency peak current mode control architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the PWM latch and turned off when the main current comparator (ICMP) resets the latch. The peak current at which comparator ICMP resets the latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier. The remote sense amplifier (DIFFAMP) produces a signal equal to the differential voltage sensed across the output capacitor and re-references it to the local IC ground reference (SGND). The FB pin receives a portion of this voltage feedback signal and compares it to the internal 0.6V reference. When the load current increases it causes a slight decrease in the FB pin voltage relative to the 0.6V reference, which in turn causes the COMP pin voltage to rise until the average inductor current is equal to the load current. The top MOSFET drivers are biased from a floating bootstrap capacitor, CB, which is normally recharged during the off-time through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. A dropout detector senses this condition and forces the top MOSFET to turn off every 10th cycle for one third of a cycle to recharge the bootstrap capacitor. Differences Between the QFN and G36 Package Options The LTC3811 is offered in two package options, a 38-pin QFN and a 36-pin SSOP The full featured QFN package . option has no leads and an exposed lead frame that needs to be soldered to the PCB, whereas the 36-pin SSOP has leads and is therefore slightly easier to solder to a PCB and to debug in the lab. The primary electrical difference between the QFN and SSOP options is the SSOP version lacks the CSOUT and PHASEMODE pins. With no CSOUT pin, the SSOP version has no provision for output voltage positioning. With no PHASEMODE input (it is internally connected to SGND), the SSOP version is limited to 2-phase and 4-phase applications.
(Refer to the Functional Diagram)
In addition to differences in pinout, another difference between the two package options is their thermal resistance. The QFN package, by virtue of its exposed lead frame, has a junction-to-ambient thermal resistance of only 34C/W, whereas the SSOP package has a thermal resistance of 100C/W. The power dissipation of the IC is a function of the input voltage, the gate charge of the external power MOSFETs and the operating frequency. The gate charge losses can be partially mitigated by using the EXTVCC input to supply power to the IC, but users should beware that high input voltage applications using very high gate charge power MOSFETs, that also need to operate at high frequency, should only be attempted using the QFN package option. More details covering thermal management are given later in this data sheet. Supplying Power to the LTC3811 The LTC3811 features several power supply input pins and multiple ways of supplying power to the gate drivers and low voltage analog control circuitry. The first method of supplying power to the IC uses the internal low dropout linear regulator (LDO) that draws power from VIN and regulates DRVCC to 6V, as shown in Figure 1. The DRVCC input supplies power to the internal gate drivers, which are capable of very high peak transient charge (1A) and discharge (5A) currents. The DRVCC supply should be decoupled to PGND with a minimum of 4.7F low ESR ceramic (X5R or better) capacitance. If multiple power MOSFETs are being driven in parallel for high current applications it is recommended that this capacitance
VIN VIN EXTVCC 4.5V
+ -
6V LDO
DRVCC GATE DRIVER SUPPLY INTVCC ANALOG SUPPLY VFB SS/TRACK 0.600V
BIAS SGND
Figure 1. Supplying Power to the LTC3811 from VIN
3811f
+ -
EA
3811 F01
15
LTC3811 OPERATION
(Refer to the Functional Diagram)
be increased to 10F Because of the high peak current . capability of the gate driver, it is essential that this capacitor be placed as close as possible to DRVCC and PGND pins, and on the same PCB layer as the IC. The INTVCC pin supplies power to all of the low voltage analog circuitry and is electrically isolated from DRVCC. The INTVCC supply is normally derived from DRVCC through an RC filter, in order to prevent gate driver supply noise from coupling into sensitive analog control circuitry. Typical values for this RC filter consist of a 1 resistor from DRVCC to INTVCC and a 0.1F low ESR ceramic capacitor from INTVCC to SGND. The INTVCC capacitor should be placed as close as possible to the INTVCC and SGND pins and on the same PCB layer as the IC. A third power supply pin, EXTVCC, serves as an auxiliary input for applications where the power dissipation in the internal LDO is excessive, or where maximum efficiency is essential. This configuration is shown in Figure 2. When the EXTVCC pin is left open or is connected to a voltage less than 4.5V, the internal 6V LDO supplies DRVCC power from VIN. If EXTVCC is tied to an external power supply greater than 4.5V, however, the 6V LDO is turned off and power is supplied to DRVCC through a 5 PMOS switch from EXTVCC. For 4.5V < EXTVCC < 7V this PMOS switch is on and DRVCC is approximately equal to EXTVCC. Using the EXTVCC pin allows the gate driver and control power to be derived from a high efficiency external source, dramatically reducing power dissipation on the IC.
VIN VIN EXTVCC AUX 5V SUPPLY DRVCC GATE DRIVER SUPPLY INTVCC ANALOG SUPPLY VFB SS/TRACK 0.600V 4.5V
Using an External 5V Supply to Measure Dynamic Quiescent Current When a voltage above 4.5V is applied to the EXTVCC pin, the internal LDO in the LTC3811 is switched off and the power is supplied by the external 5V power supply as shown in Figure 2. Under these conditions, the quiescent current at the VIN pin of the IC is very low (less than 1mA), and most of the current required to power the analog control circuitry and the gate drivers flows into the EXTVCC pin. As a result, this auxiliary supply can be used as a diagnostic tool in order to measure the total current for thermal calculations. In order to match the actual condition when the internal LDO is on, the voltage applied to EXTVCC when the measurements are taken should be 6V (the same as the regulated LDO output voltage). Once the total quiescent current for the application is known, the power dissipation, PD, on the IC will be approximately IEXTVCC times VIN, since the gate drive current and control circuitry quiescent current would be required to flow through the VIN pin. The junction temperature of the IC can then be estimated using the following wellknown formula: TJ = TA + (PD * RJA) If the maximum junction temperature is close to the Absolute Maximum Rating for the particular device being used, the use of an auxiliary supply and the EXTVCC pin may be required. Alternatively, lower gate charge MOSFETs should be used or the switching frequency should be reduced. Operation at Low Supply Voltage
+ -
6V LDO
BIAS SGND
EA
The LTC3811 control circuit has a minimum input voltage of 4.5V, making it a good choice for applications that experience low supply conditions. However, care should be taken to determine the minimum gate drive supply voltage in order to choose the optimum power MOSFETs. Important parameters that can affect the minimum gate drive voltage are the minimum input voltage (VIN), the LDO dropout voltage, and the EXTVCC supply voltage, if an external gate drive supply is being used.
3811 F02
Figure 2. Supplying Power to the LTC3811 from EXTVCC
3811f
16
+ -
LTC3811 OPERATION
(Refer to the Functional Diagram)
If the internal LDO is supplying power to the gate driver and the input voltage is low enough for the LDO to be in dropout, then the minimum gate drive supply voltage is: VDRVCC = VIN(MIN) - VDROPOUT The LDO dropout voltage is a function of the total gate drive current and the quiescent current of the IC (typically 10mA). A curve of dropout voltage vs output current for the LDO is shown in the Typical Performance Characteristics. The temperature coefficient of the LDO dropout voltage is approximately +4000ppm/C. The total Q-current (IQ(TOT)) flowing in the LDO is the sum of the controller quiescent current (typically 10mA) and the total gate charge drive current. IQ(TOT) = IQ + QG(TOT) * f If an external supply is being used to supply power to the gate driver through the EXTVCC pin, then the minimum gate drive supply voltage is: VDRVCC = VEXTVCC - IQ(TOT) * REXTVCC The resistance of the internal EXTVCC PMOS switch is typically 5 at 25C and has a temperature coefficient of approximately 3400ppm/C. After the calculations have been completed, it is important to measure the gate drive waveforms (BG-to-PGND and TG-to-SW) and the gate driver supply voltage (DRVCC-toPGND) over all operating conditions (low VIN, mid VIN, and high VIN, as well as from light load-to-full load) to ensure adequate power MOSFET enhancement. Consult the power MOSFET data sheet to determine the actual RDS(ON) for the measured VGS, and verify your thermal calculations by measuring the component temperatures using an infrared camera. On/Off Control Using the RUN Pin The two channels of the LTC3811 can be independently turned on and off using the RUN1 and RUN2 pins. Pulling either of these pins low shuts down the main control loop for that channel. Pulling both pins low disables both controllers and most of the internal circuitry, including the DRVCC low dropout regulator (LDO). In shutdown mode (both RUN pins low) the LTC3811 typically draws only 20A of current.
The RUN pins may be externally pulled up or driven directly by logic. Be careful not to exceed the 7V absolute maximum rating on this pin. Soft-Start and Tracking Using the SS/TRACK Pin The start-up of each controller's output voltage VOUT is normally controlled by the voltage on the SS/TRACK pin for that channel. The SS/TRACK pin represents a 2nd noninverting input to the error amplifier, as shown in Figure 3. The error amplifier is configured so that the lower of the two noninverting inputs (the SS/TRACK pin or the 0.6V reference) controls the feedback loop. That is, when the voltage on the SS/TRACK pin is less than the 0.6V internal reference, the LTC3811 regulates the FB pin voltage to be approximately equal to the SS/TRACK pin voltage instead of the internal 0.6V reference. This allows the user to connect a capacitor from the SS/TRACK pin to SGND to program the soft-start of the power supply output. An internal 2.5A current source charges this capacitor, creating a voltage ramp on the SS/TRACK pin. As the SS/ TRACK pin voltage rises from 0V to 0.6V, the output voltage, VOUT, rises smoothly from 0V to its final value. Once the soft-start interval is over, the internal 2.5A current source will continue to charge the SS/TRACK capacitor up to a maximum voltage equal to INTVCC. Alternately, the SS/TRACK pin can be used to force the start-up of VOUT to track the voltage of another supply. Typically, this requires connecting the SS/TRACK pin to an external divider from the other supply to ground (see Applications Information).
INTVCC INTVCC
Q2 Q4 Q3
VFB
INTVCC 2.5A 0.6V Q1 Q5 SHDN M1
3811 F03
SS/TRACK
Figure 3. Simplified LTC3811 Error Amplifier Input Stage
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17
LTC3811 OPERATION
(Refer to the Functional Diagram)
The SS/TRACK pin has an internal open-drain NMOS pulldown transistor that turns on when the corresponding RUN pin is pulled low to disable that controller, when the voltage on the DRVCC pin is below 3.7V (the rising undervoltage lockout threshold), or during an overtemperature condition. During an undervoltage lockout, UVLO, or overtemperature, OT, condition, both controllers are disabled and the external MOSFETs are held off. In multiphase applications, one master error amplifier is used to control all of the phase current comparators. The FB pins for the unused error amplifiers are connected to INTVCC in order to three-state these amplifier outputs. As a result, the SS/TRACK pins for the unused error amplifiers should be left open. Programming the Operating Mode The MODE/SYNC pin serves to either program the operating mode or to synchronize the operating frequency to an external clock using the internal PLL. Connecting the MODE/SYNC pin to ground programs pulse-skip mode operation and connecting the pin to INTVCC programs forced continuous operation, as shown in Table 1. In pulseskip mode the inductor current is not allowed to reverse, resulting in discontinuous mode, DCM, operation at light load. Pulse-skip mode is ideal for applications where light load efficiency is a higher priority than transient response. In forced continuous mode, the synchronous switch turns on after the primary switch turns off and remains on for the duration of the clock cycle, regardless of the load current. Forced continuous mode is ideal for applications needing optimized transient response, or for systems where constant frequency operation is important. Certain applications can result in the startup of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent a reversal of current in the inductor under these conditions, pulse-skip operation is asserted at startup until the FB pin reaches the lower PGOOD threshold of 0.54V. Once the FB pin voltage exceeds 0.54V, the operating mode is determined by the voltage on the MODE/SYNC pin. When the operating frequency of the converter is synchronized to an external clock using the MODE/SYNC pin, the
operating mode will always be forced continuous. Forcing continuous mode operation results in constant frequency operation and a more predictable noise spectrum from the converter.
Table 1
MODE/SYNC SGND INTVCC External Clock OPERATING MODE Pulse-Skip Forced Continuous Forced Continuous DESCRIPTION DCM Operation at Light Load CCM from No Load to Full Load Operating Frequency Synchronized Using Internal PLL (CCM)
Frequency Selection and the Phase-Lock Loop The selection of the switching frequency is a tradeoff between efficiency, transient response and component size. Low frequency operation increases efficiency by reducing MOSEFT switching losses, but requires a larger inductor and output capacitor to maintain low output ripple. The switching frequency of the LTC3811's controllers can be selected using the PLL/LPF pin. If the MODE/SYNC pin is not being driven by an external clock, the PLL/LPF pin can be tied to SGND, left open or tied to INTVCC to select 250kHz, 500kHz or 750kHz, respectively, as shown in Table 2.
Table 2
PLL/LPF SGND Floating INTVCC RC Filter to SGND MODE/SYNC 0V or INTVCC (DC) 0V or INTVCC (DC) 0V or INTVCC (DC) Connected to External Clock FREQUENCY 250kHz 500kHz 750kHz Phase Locked to External Clock
A phase-lock loop is available on the LTC3811 to synchronize the internal oscillator to an external clock source connected to the MODE/SYNC pin. In this case, a series RC network connected from the PLL/LPF pin to SGND serves as the PLL's loop filter. The PLL/LPF pin is both the output of the phase detector and the input to the voltage controlled oscillator, VCO. The LTC3811 phase detector adjusts the voltage on the PLL/LPF pin to align the rising edge of TG1 to the leading edge of the external clock signal. The turn-on of the second channel TG2 will depend upon the voltage on the PHASEMODE pin as shown in the Electrical Characteristics.
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LTC3811 OPERATION
(Refer to the Functional Diagram)
The typical capture range of the LTC3811's PLL is approximately 125kHz to 1.1MHz, with a guarantee over all manufacturing variations to be between 175kHz and 900kHz. The amplitude of the sync pulse to the LTC3811 should be greater than 1.8V and the minimum pulse width should be greater than 200ns. Using the CLKOUT and PHASEMODE Pins in Multiphase Applications The LTC3811 features two pins (CLKOUT and PHASEMODE) that allow multiple LTC3811 ICs to be daisy-chained together in multiphase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single high current output or even separate outputs. The PHASEMODE pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and CLKOUT, as summarized in Table 3. The phases are calculated relative to the zero degrees, defined as the rising edge of the top gate driver output of channel 1, TG1. The PHASEMODE input comparators are referenced to an internal divider from INTVCC that has 33% and 67% INTVCC thresholds. For 6-phase operation, connect PHASEMODE to an external divider from INTVCC with equal value resistors (e.g., 100k), so that PHASEMODE is always 50% of INTVCC.
Table 3
# PHASES 2 3 4 6 IC # 1 1 2 1 2 1 2 3 1 2 3 4 5 6 PHASEMODE 0V INTVCC 0V 0V 0V 50% INTVCC 50% INTVCC 50% INTVCC 50% INTVCC 50% INTVCC 0V 50% INTVCC 50% INTVCC 50% INTVCC CLKOUT CONNECTS TO N/A MODE/SYNC of IC # 2 N/A MODE/SYNC of IC # 2 N/A MODE/SYNC of IC # 2 MODE/SYNC of IC # 2 N/A MODE/SYNC of IC # 2 MODE/SYNC of IC # 3 MODE/SYNC of IC # 4 MODE/SYNC of IC # 5 MODE/SYNC of IC # 6 N/A
Remote Sensing Using the Differential Amplifier The LTC3811 has a differential amplifier for true remote sensing of the output voltage. The sensing connections should be returned from the load back to the differential amplifier's inputs through a common, tightly coupled pair of PCB traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PCB traces, as well as ground loop disturbances. The differential amplifier output signal is typically divided down and compared with the internal precision 0.6V voltage reference by the error amplifier. The differential amplifier utilizes four precision internal resistors to enable instrumentation-type measurement of the output voltage. The amplifier has a gain of 1.000, contains a CMOS rail-to-rail output stage, and is optimized for low input offset and high bandwidth. The output voltage is set by an external resistive divider according to the following formula: R2 VOUT = 0.6 * 1+ R1 where R2 and R1 are the upper and lower divider resistors, respectively. The differential amplifier was optimized for divider currents in the range of 100A to 600A, meaning that R1 in the equation above should be 1k to 6k. Using the LTC3811 Operational Error Amplifiers in Multiphase Applications The LTC3811 error amplifiers are true operational amplifiers, meaning that they have high DC gain and low output impedance. In previous generations of multiphase controllers, such as the LTC1628 family, the error amplifiers were transconductance amplifiers, meaning that they could be connected in parallel for multiphase applications. Multiphase applications using the LTC3811 will use one operational error amplifier as the master and will disable all of the slave phase error amplifiers. Typically, the channel 1 amplifier for phase = 0 will be used as the master and phases 2 through n (up to 12 phases) will serve as slaves. To disable the slave error amplifiers but still use their current comparators and power stages, connect the
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19
LTC3811 OPERATION
(Refer to the Functional Diagram)
ONLY PGOOD PIN FOR MASTER CHANNEL IS USED (FLOAT SLAVE CHANNEL PGOOD PINS) MASTER LTC3811 INTVCC PGOOD1 PGOOD2 FB2 DIFF/IN+ DIFF/IN- RUN1 DIFF/OUT RUN2 FB1 COMP1 SS/TRACK1 COMP2 SS/TRACK2 CLKOUT SGND
INDIVIDUAL INTVCC AND DRVCC PINS LOCALLY DECOUPLED (DRVCC NOT SHOWN)
VOUT+ VOUT- MASTER DIFFERENTIAL AMPLIFIER USED TO DRIVE CHANNEL 1 ERROR AMPLIFIER SLAVE CHANNEL FB PINS ALL CONNECTED TO LOCAL INTVCC PINS TO DISABLE ERROR AMPLIFIERS
the amplitude of those for one regulator to be drawn from the input capacitor. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor. With multiphase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 5 illustrates the benefits of multiphase operation. Current ripple at the input is reduced by a factor of 1.41 (square root of 2), reducing the size and cost of the input capacitor. In addition, since power losses are proportional to IRMS2, significant efficiency improvements in the input power path components (batteries, switches, protection circuitry and PCB traces) can be achieved. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current.
IL 5A/DIV
ON/OFF CONTROL ALL SS/TRACK PINS CONNECTED TOGETHER
SLAVE SYNC LTC3811 INTVCC PGOOD1 FB2 PGOOD2 FB1 RUN1 COMP1 RUN2 COMP2 SS/TRACK1 SS/TRACK2 CLKOUT SGND
ALL RUN PINS CONNECTED TOGETHER
SLAVE SYNC LTC3811 PGOOD1 INTVCC PGOOD2 FB2 RUN1 FB1 RUN2 COMP1 COMP2 SS/TRACK1 SS/TRACK2 SGND
3811 F04
SLAVE CHANNEL COMP PINS ALL CONNECTED TO MASTER CHANNEL COMP PIN
SGND BUS ISOLATED FROM PGND AND INDEPENDENTLY ROUTED TO NEGATIVE TERMINAL OF OUTPUT CAPACITOR
Figure 4. LTC3811 Error Amplifier Configuration for Multiphase Operation
SW1 10V/DIV SW2 10V/DIV VIN = 12V VOUT = 1.5V IOUT = 16A 1s/DIV
3811 G41
FB pin of a slave phase to INTVCC. As shown in the Functional Diagram, a comparator detects when the FB pin is shorted to INTVCC and three-states this amplifier's output and input. The COMP pins for all of the phases can then be shorted together in order to provide compensation for the feedback loop, as shown in Figure 4. Theory and Benefits of Multiphase Operation Why the need for multiphase operation? Up until the multiphase family, constant frequency dual switching regulators operated both channels in phase (i.e., singlephase operation). This means that both switches turned on at the same time, causing current pulses of up to twice
Figure 5. 2-Phase, Single Output Current Sharing Waveforms
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator's relative duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 6 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the
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LTC3811 OPERATION
(Refer to the Functional Diagram)
x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 6, the zero output ripple current is obtained when: VOUT k = where k = 1, 2, ..., N - 1 VIN N So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results. Accepting larger values of IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages.
1.0 0.9 0.8 0.7 IO(P-P) 0.6 VO/fL 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
lockout or overtemperature condition. When the FB pin voltage is within the 10% window, the internal PGOOD MOSFET is turned off and the pin is normally pulled up by an external resistor. The absolute maximum voltage rating of the PGOOD pins is 7V. The PGOOD logic contains separate filters depending on whether the controller is entering or exiting a fault condition. When the FB pin is exiting a fault condition (such as during normal output voltage start-up, prior to regulation), the PGOOD pin will remain low for an additional 30s. This allows the output voltage to reach steady-state regulation and prevents the enabling of a heavy load from re-triggering a UVLO condition. When the FB pin is entering either an undervoltage, UV, or overvoltage, OV, fault condition, the PGOOD pin will remain high 130s after the onset of the fault. This non-integrating filter prevents noise or short duration overload conditions from triggering the PGOOD outputs and causing a false system reset. Figure 7 illustrates the timing diagram for a hypothetical undervoltage event on the FB pin, and the resulting PGOOD waveform. In multiphase applications, one error amplifier is used to control all of the phase current comparators. In addition, since the FB pins for the unused error amplifiers are connected to INTVCC (in order to three-state these amplifiers), the PGOOD outputs for these amplifiers will be asserted. In order to prevent falsely reporting a fault condition, the
0.7 0.6 0.5 VFB (V) 0.54V = UV THRESHOLD 0.66V = OV THRESHOLD
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
0.4 0.3 0.2 0.1
3811 F06
Figure 6. Normalized Peak Output Current vs Duty factor [IRMS 0.3(IO(P-P))]
Power Good Pins (PGOOD1, PGOOD2) Each PGOOD pin is connected to the open drain of an internal N-channel pull-down MOSFET. The MOSEFT turns on and pulls the PGOOD pin low when the corresponding FB pin is outside a 10% window around the 0.6V reference voltage. The PGOOD pin is also pulled low when the corresponding RUN pin is low, or during an undervoltage
VPGOOD (V)
0 5
TIME t < 30s 130s 30s
0
TIME
3811 F07
Figure 7. PGOOD Filter Timing Diagram
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LTC3811 OPERATION
(Refer to the Functional Diagram)
PGOOD outputs for the unused error amplifiers should be left open. Only the PGOOD output for the master control error amplifier should be connected to the fault monitor. Fault Conditions: Current Limit and Foldback One of the main advantages of the LTC3811 is the fact that the maximum inductor current is inherently limited due to the use of peak current mode control. The maximum sense voltage is controlled by the voltage on the RNG pins and the maximum DC output current is: ILIMIT = VSENSE(MAX) RSENSE - 1 * IL 2
Under short-circuit conditions with very low duty cycles, the LTC3811 may begin to skip pulses in order to limit the maximum current. In this situation the bottom MOSFET will be dissipating most of the power; however this will be less than in normal operation at maximum load. In this case the short circuit ripple current is determined by the minimum on-time, tON(MIN), of the LTC3811 (about 65ns), the input voltage, and the inductor value, according to the following equation: IL(SC) = tON(MIN) * VIN L
The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of the current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power losses in the converter. To further limit current in the event of an output short-circuit to ground, the LTC3811 includes foldback current limiting. When the FB pin falls below 0.3V (50% of its nominally regulated value), the foldback circuit is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short circuit condition. If the FB pin reaches 0V, the peak current sense threshold will be reduced to 30% of its maximum value. The foldback current limit transfer function is shown in Figure 8.
60 MAXIMUM SENSE THRESHOLD (mV) 55 50 45 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 FB VOLTAGE (mV) 600 700 RNG = INTVCC
The resulting short-circuit current is 0.3 * VSENSE(MAX) 1 ISC = - * IL(SC) RSENSE 2 Depending upon the ratio of the DC value of the current limit to the maximum load current and the percentage ripple current in the inductor, it is possible that the converter will operate in discontinuous mode when VFB = 0V (a so-called "dead short"). In this case, the short-circuit current of the converter will be: ISC = IL(SC) 2 = tON(MIN) * VIN 2*L
In order for the converter to start up properly with a nonlinear load, the foldback current limiting circuit in the LTC3811 is disabled during the initial soft-start interval. When the FB pin voltage reaches 0.54V, the soft-start interval is terminated and the foldback circuit is enabled. In the event the converter is turned on into a shorted load, the foldback circuit will be disabled until the SS/TRACK pin reaches 0.54V. This ensures that the converter will still limit the maximum current to a safe level and reduce the peak power dissipated with a shorted load.
3811 G31
Figure 8. Current Foldback Charactistic
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LTC3811 APPLICATIONS INFORMATION
Duty Cycle Considerations The duty cycle for a buck converter is well known:
LTC3811 COMP
V D = OUT = tON * f VIN Rearranging, the minimum on-time for a given application can be calculated: tON(MIN) = VOUT VIN(MAX ) * f
VOUT FB R1 SGND
3811 F09
R2 COUT
DIVIDER AND COMPENSATION COMPONENTS PLACED NEAR FB, SGND AND COMP PINS
For a given input and output voltage, it is important to know how close the minimum on-time of the application comes to the minimum on-time of the control IC. The LTC3811 has a typical minimum on-time of 65ns, allowing both high input to output ratios and high frequency operation. In an application circuit, if the IC's minimum on-time exceeds the value required in the duty cycle equations, the converter will begin to skip pulses and operate at a fraction of the intended frequency. This frequency division will result in higher current and voltage ripple and is of particular concern in forced continuous applications with low ripple currents at light loads. Setting the Output Voltage The LTC3811 output voltages are each set by external feedback resistor dividers, according to the following equation: R2 VOUT = 0.6V * 1+ R1 Care should be taken to place the output divider resistors and the compensation components as close as possible to the IC FB and SGND pins, in order to prevent switching noise from coupling into the signal path. This configuration is shown in Figure 9. The top of R2 is normally routed to the top of the output capacitor, or to the output of the differential amplifier, if remote sensing is being employed. Because the common mode range of the current comparator input stages is 0V to 3.5V, the output voltage range is limited from 0.6V to 3.3V.
Figure 9. Output Divider and Compensation Component Placement
Sensing the Output Voltage with a Differential Amplifier The LTC3811 includes a low offset, unity gain, high bandwidth differential amplifier for applications that require true remote sensing. Sensing both SENSE+ and SENSE- greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. The LTC3811 differential amplifier has a typical output slew rate of 8V/s and has rail-to-rail output drive capability. The amplifier is configured for unit gain, meaning that the difference between SENSE+ and SENSE- is translated to DIFFOUT, relative to SGND. Care should be taken to route the SENSE+ and SENSE- PCB traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, the SENSE+ and SENSE- traces should be shielded by a low impedance ground plane to maintain signal integrity. Choosing the Inductor Value and Saturation Current Rating The operating frequency and inductor value are interrelated in that higher operating frequencies allow the use of smaller inductors and capacitors. Higher frequency operation also results in higher switching and gate drive losses, so a basic tradeoff exists between size and efficiency.
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LTC3811 APPLICATIONS INFORMATION
For CCM operation, the inductor value can be chosen using the following equation: L= VOUT V 1- OUT f * IL VIN(MAX) Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core materials exhibit "hard" saturation, meaning that the inductance collapses abruptly when the peak current capability is exceeded. This results in an abrupt increase in inductor ripple current and output voltage ripple. Do not allow the core to saturate! Programming the Maximum Sense Voltage Using the RNG Pin The RNG pin can be used in two different ways in order to program the maximum peak current sense voltage. The easiest way to program the peak sense voltage is to tie the RNG pin to either ground or INTVCC. Connecting the RNG pin to ground results in a 24mV peak sense voltage and connecting it to INTVCC programs in a 50mV peak sense voltage. Alternately, an external resistor divider from INTVCC to ground can be used to set the RNG pin between 0.6V and 2V, resulting in a nominal peak sense voltage range of 24mV to 85mV. Figure 10 illustrates the transfer function from the RNG pin to the peak sense voltage, which closely follows the following equation for 0.6V < VRNG < 2V: VSENSE(MAX) = 0.0436 * VRNG - 0.0022 In general, the accuracy of the SENSE pin threshold will scale with the peak sense voltage defined by the RNG
MAXIMUM CURRENT SENSE THRESHOLD (mV) 90 80 70 60 50 40 30 20 10 0 0.5 0.7 0.9 1.1 1.3 1.5 VRNG VOLTAGE (V) 1.7 1.9
3811 G30
Choosing a larger value of IL allows the use of a lower value inductor, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting the ripple current is 40% to 50% of the maximum output current, or: IL = 0.4 * IOUT(MAX) The inductor saturation current rating needs to be higher than the peak inductor current during an overload condition. If IOUT(MAX) is the maximum rated load current, then the maximum overload current, IMAX, would normally be chosen to be some factor (e.g., 30%) greater than IOUT(MAX): IMAX = 1.3 * IOUT(MAX) IL(PK) = IMAX + 1 * IL 2
For a 40% ripple application, the minimum saturation current rating of the inductor would therefore be: IL(PK) = 1.5 * IO(MAX) In other words, for an application with 40% inductor ripple current and a maximum output current 30% greater than the full load current, the inductor's saturation current rating needs to be at least 1.5 times the maximum output current. Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.
Figure 10. Maximum Current Sense Threshold vs RNG Pin Voltage
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LTC3811 APPLICATIONS INFORMATION
pin. For applications requiring maximum current limit accuracy, a higher peak sense voltage (e.g., 85mV) should be chosen. An additional benefit of a higher peak SENSE pin threshold is a slight reduction in the minimum ontime of the controller. That is, for a given ripple current in the inductor, a higher peak sense voltage results in higher SENSE pin dV/dt, speeding up the input stage of the current comparator slightly. For applications where high efficiency and tight current limit accuracy are both important, the peak current sense voltage can be reduced to as low as 24mV. In multiphase applications, only one error amplifier is used to control all of the phase current comparators. As a result, in multiphase applications all of the RNG pins should all be tied to the same potential, in order to program the same power stage gm for each phase. SENSE+ and SENSE- Pins The common mode input voltage range of the current comparators is 0V to 3.5V. Continuous linear operation is provided throughout this range, allowing output voltages between 0.6V (the reference input to the error amplifiers) and 3.3V. The SENSE+ and SENSE- pins are also the inputs to the voltage positioning current sense gm amplifier. Under normal operation, a small current of about 1.5A flows out of the SENSE inputs and represents the total base current of the two vertical PNP input stages (one in the current comparator and one in the voltage positioning current sense amplifier). When the common mode voltage is lower than about 0.4V, the current flowing out of the SENSE pins increases, up to about 2.2A at VSENSE = 0V. Figure 11 illustrates the change in the SENSE pin current as a function of common mode voltage. Sensing Techniques Using Low Value Resistors For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. For today's highest current density solutions, however, the value of the sense resistor can be less than 1m and the peak sense voltage can be as low as 24mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the sense resistor's parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 12. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled in the sense traces on the PCB. A typical filter consists of two series 10 resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns.
2.5
SENSE PIN CURRENT (A)
2.0 1.5
1.0
0.5
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMMON MODE VOLTAGE (V)
3811 G33
Figure 11. SENSE Pin Input Bias Current vs Common Mode (Output) Voltage
VIN DRVCC LTC3811 BOOST TG SW BG PGND SENSE+ SENSE- SGND RF CF RF
VIN
SENSE RESISTOR PLUS PARASITIC INDUCTANCE RS ESL VOUT
CF * 2RF = ESL/RS POLE-ZERO CANCELLATION
3811 F12
FILTER COMPONENTS PLACED NEAR SENSE PINS
Figure 12. Using a Resistor to Sense Current with the LTC3811
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LTC3811 APPLICATIONS INFORMATION
This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 13 illustrates the voltage waveform across a 1.5m Panasonic metal strip resistor (ERJ-M1WTJ1M5U). The waveform is the superposition of a purely resistive component and a purely inductive component and was measured with a single low impedance scope probe through a BNC connected directly across the sense resistor terminals. Based on additional measurements of the inductor ripple current and the on- and off-times of the primary switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: I I VESL(STEP) = ESL * L + L tON tOFF If the RC time constant is chosen to be exactly the same as the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 14. For applications using low maximum sense voltages, check the sense resistor manufacturer's data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor using a low impedance connection to extract the magnitude of the ESL step and use the equation above to determine the proper filter time constant, keeping the two filter resistor values equal and less than about 200 each. Finally, place these filter components close to the IC and run the positive and negative sense traces parallel to each other all the way to the sense resistor. Inductor DCR Sensing For applications requiring the highest possible efficiency, the LTC3811 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 15. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1m for today's low value, high current inductors. If the external RC time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR. Check the manufacturer's data sheet for specifications regarding the inductor DCR in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter.
VIN 250ns/DIV
3811 F13
10mV/DIV
VIN DRVCC LTC3811 BOOST TG SW BG PGND SENSE+ R1 = R2 R2 C1 R1 * C1 = L/DCR R1 SW INDUCTOR L DCR VOUT
Figure 13. Current Sense Waveform for the Circuit in Figure 33
10mV/DIV SENSE- SGND
3811 F15
250ns/DIV
3811 F14
Figure 14. Waveform at the SENSE+ and SENSE- Pins Using RC - L/R Time Constant Cancellation
FILTER COMPONENTS SHOULD BE PLACED NEAR SENSE+, SENSE- PINS
PLACE R1 NEAR INDUCTOR TO MINIMIZE SW NODE NOISE COUPLING
Figure15: Current Mode Control Using the Inductor DCR
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LTC3811 APPLICATIONS INFORMATION
The value of the resistors in the RC filter is a tradeoff between power dissipation and DC accuracy. The power loss on R1 is: R1 for a buck converter. If the value of the filter resistor is too low, its power dissipation will rise, resulting in a larger package size and decreased efficiency at light load. If the value of the filter resistor is too high, the input bias current flowing out of the SENSE+ pin (approximately 1.5A) could cause the voltage drop across the resistor to be the same order of magnitude of the peak sense voltage, which is also undesirable. A good balance is to use a resistor value of about 1k. An additional 1k resistor (R2) in the SENSE- path is used to compensate for the drop in the SENSE+ path, and ideally these two resistors (R1 and R2) should match one another. In general, the larger the sense voltage range is, the smaller the percentage error due to a mismatch in the filter resistor IR drops. The current comparators were designed for low offset and high speed, specifically for applications requiring a small peak sense voltage. Gate Drive Power Supply Considerations The LTC3811 user has a choice of how to supply power to the gate drivers and low voltage analog control circuitry. The first of these is to use the internal low dropout linear regulator, LDO, to draw power from VIN and regulate DRVCC to 6V. The second way of supplying power to the gate drivers and analog control circuitry is through the EXTVCC pin. The choice of which supply path to use depends upon system flexibility, power dissipation and the maximum junction temperature in the application. The internal DRVCC LDO is capable of sourcing up to 100mA, allowing the user to connect multiple power MOSFETs in parallel on both channels for the high power density applications. High input voltage applications in which multiple large MOSFETs are being driven at high frequencies, however, may cause the maximum junction temperature rating for the LTC3811 to be exceeded. PR1 = In general, there are three potential sources of power dissipation in the LTC3811: 1. The quiescent current consumed by all of the analog control circuitry connected to INTVCC 2. Gate drive losses 3. Losses in the LDO when power is being supplied from VIN The steady-state quiescent current of the IC is typically 10mA and flows into the INTVCC pin, either through the LDO from VIN or through an auxiliary power supply connected to the EXTVCC pin. The second source of power dissipation is the gate drivers connected to DRVCC. The lower MOSFET gate drivers are directly connected to DRVCC and the upper ones are connected to DRVCC through the bootstrap diode and floating supply capacitor CB (refer to Functional Diagram). The gate driver current requirement depends upon the number of MOSFETs being driven, their total gate charge, QG(TOT), and the operating frequency, f, of the converter. The total current required by the low voltage circuitry is the sum of the DC quiescent current and the gate drive current. IVCC = 10mA + QG(TOT) * f If the internal LDO in the LTC3811 is used to supply power to DRVCC and INTVCC, care should be taken to ensure that the total low voltage current doesn't exceed the 100mA limit for the LDO. Assuming that DRVCC = EXTVCC = INTVCC = 6V, power dissipation due to the quiescent current and gate drive losses is: PVCC = 6V * (10mA + QG(TOT) * f) The third source of power dissipation occurs in the LDO, which supplies power to the DRVCC pin when EXTVCC is less than 4.7V. When power is being drawn from VIN the power dissipated in the LDO is: PLDO = (VIN - VDRVCC) * (10mA + QG(TOT) * f)
(VIN - VO) * VO
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LTC3811 APPLICATIONS INFORMATION
The total power dissipation is the sum of these two and the junction temperature can then be estimated using the following equation: TJ = TA + (PVCC + PLDO) * RJA As an example, consider a 2-phase, single-output application with a 12V input voltage and a 1.2V output at up to 30A (15A/phase), using the QFN version of the LTC3811. The upper power MOSFETs are the Renesas RJK0305DPB (one per phase) and the lower power MOSFETs are the RJK0301DPB (one per phase). The upper MOSFETs have a typical RDS(ON) = 10m at VGS = 4.5V and a typical QG = 8nC. The lower MOSFETs have a typical RDS(ON) = 3m at VGS = 4.5V and a typical QG = 32nC. The total gate charge is therefore 80nC and the operating frequency is 500kHz. With a maximum ambient temperature of 70C and a thermal resistance of 34C/W for the QFN package, IDRVCC = 10mA + 500kHz * 80nC = 50mA PDRVCC = 6V * (10mA + 500kHz * 80nC) = 300mW PLDO = (12V - 6V) * (10mA + 500kHz * 80nC) = 300mW TJ = 70C + (0.3 + 0.3) * 34C/W = 90C A 20C rise in the junction temperature and a maximum LDO current of 50mA are acceptable numbers but could be improved upon by using the EXTVCC pin to supply power to the gate drivers. The use of an auxiliary supply connected to the EXTVCC pin would reduce the junction temperature rise by a factor of 2, resulting in a max junction temperature of: TJ = 70C + 0.3 * 34C/W = 80C For applications where the internal LDO is being used to supply power to the IC, to prevent the maximum junction temperature from being exceeded the input supply current should be monitored at maximum VIN in continuous conduction mode (i.e., with MODE/SYNC connected to INTVCC). Using the EXTVCC Pin to Supply Power to the LTC3811 The LTC3811 contains an internal P-channel MOSFET switch connected between the EXTVCC and DRVCC pins. When the voltage applied to EXTVCC exceeds 4.5V, the internal LDO is turned off and the PMOS switch turns on, connecting the EXTVCC pin to the DRVCC pin and thereby supplying the internal analog and digital circuitry and MOSFET gate drive power. Do not apply greater than 7V to the EXTVCC pin (its absolute maximum rating) and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an external voltage source is applied to the EXTVCC pin when the VIN supply is not present, a diode can be placed in series with the LTC3811's VIN pin and a Schottky diode between the EXTVCC pin and the VIN pin, to prevent current from backfeeding into VIN through the PMOS body diodes. Significant energy gains can be realized by powering DRVCC and INTVCC from an auxiliary supply, since the VIN current resulting from the driver and analog control circuitry currents will be scaled by the ratio: Duty Cycle/Efficiency The following list summarizes the three possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause DRVCC and INTVCC to be powered from the internal 6V LDO, resulting in a significant efficiency penalty and excess power dissipation at high input voltages. 2. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range it may be used to power EXTVCC, provided it is capable of satisfying the gate drive and control IC current requirements. VIN must be greater than or equal to the voltage applied to the EXTVCC pin. 3. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage which has been boosted to greater than 4.5V but less than 7V. This can be done with a capacitive charge pump shown in Figure 16. Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3811: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch.
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LTC3811 APPLICATIONS INFORMATION
CIN VIN TG1 LTC3811 EXTVCC SW1 BG1 PGND L1 VN2222LL RSENSE BAT85
+
VIN
+
0.22F BAT85
PMAIN =
VOUT (IMAX )2 RDS(ON) (1+ ) + VIN
BAT85
(VIN)2 IMAX (RDR )(CMILLER ) * 2
1 1 + (f) VINTVCC - VTHMIN VTHMIN PSYNC = VIN - VOUT (IMAX )2 (1+ )RDS(ON) VIN
VOUT
+
D1
COUT
3811 F16
Figure 16. Capacitive Charge Pump for EXTVCC
The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 6V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs should be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers' data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the Gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN - VOUT VIN
where is the temperature dependency of RDS(ON) and RDR (approximately 2) is the effective top gate driver resistance at the MOSFET's Miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. The optional Schottky diode, D1, shown in Figure 16 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 1% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance.
Synchronous Switch Duty Cycle =
The MOSFET power dissipations at maximum output current are given by:
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LTC3811 APPLICATIONS INFORMATION
CIN and COUT Selection In continuous mode, the drain current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 17 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or: VOUT k = where k = 1, 2, ..., N - 1 VIN N So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 17, the local maximum input RMS capacitor currents are reached when: VOUT 2k - 1 = where k = 1, 2, ..., N 2N VIN These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number, N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase
RMS INPUT RIPPLE CURRNET 0.6 0.5 DC LOAD CURRENT 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
3811 F17
Figure 17. Normilized Input RMS Ripple Current vs Duty Factor for 1 to 6 Output Stages
system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady-state output ripple (VOUT) is determined by: 1 VOUT IRIPPLE ESR + 8NfCOUT where f = operating frequency of each stage, N is the number of phases, COUT = output capacitance and IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with IL = 0.4IOUT(MAX)/N assuming: COUT required ESR < 2N(RSENSE) and COUT > 1/(8Nf)(RSENSE) The emergence of very low ESR ceramic capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the LTC3811's true operational error amplifier allows a much wider selection of output capacitor types. The ability to
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LTC3811 APPLICATIONS INFORMATION
use type III compensation effectively removes constraints on output capacitor ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling and bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. Tracking and Soft-Start (SS/TRACK Pins) The start-up of each VOUT is controlled by the voltage on the respective SS/TRACK pin. When the voltage on the SS/TRACK pin is less than the internal 0.6V reference, the LTC3811 regulates the VFB pin voltage to the voltage on the SS/TRACK pin instead of 0.6V. The SS/TRACK pin can be used to program an external soft-start function or to allow VOUT to "track" another supply during start-up. Soft-start is enabled by simply connecting a capacitor from the SS/TRACK pin to ground, as shown in Figure 18. An internal 2.5A current source charges up the capacitor, providing a linear ramping voltage at the SS/TRACK pin. The LTC3811 will regulate the VFB pin (and hence VOUT) according to the voltage on the SS/TRACK pin, allowing VOUT to rise smoothly from 0V to its final regulated value. The total soft-start time will be approximately: t SS = C SS * 0.6V 2.5A
Alternatively, the SS/TRACK pin can be used to track two (or more) supplies during start-up, as shown qualitatively in Figures 19a and 19b. To do this, a resistor divider should be connected from the master supply (VX) to the SS/TRACK pin of the slave supply (VOUT), as shown in Figure 20. During start-up VOUT will track VX according to the ratio set by the resistor divider: VOUT R TRACKA R A + RB = * VX RA R TRACKA + R TRACKB For coincident tracking (VOUT = VX during start-up), RA = RTRACKA RB = RTRACKB Note that the small SS/TRACK charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistor divider values to be small enough to make this error negligible. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST and SW pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from DRVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch
LTC3811 SS/TRACK CSS SGND
3811 F18
Figure 18. Using the SS/TRACK pin to Program Soft-Start
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LTC3811 APPLICATIONS INFORMATION
node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VDRVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Overvoltage Protection The LTC3811 contains a comparator that monitors the FB pin voltage for potential overvoltage conditions. This comparator (OV in the Functional Diagram) detects when the FB pin voltage exceeds 0.66V, or is 10% above nominal regulation. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on. For an overvoltage condition that persists, the inductor current will reverse until the negative current limit of the converter is reached. If the OV condition terminates VOUT will return to regulation and normal operation automatically resumes. The OV signal that controls the top and bottom MOSFET switching does not propagate through the PGOOD filter before action is taken. The OV comparator is capable of sensing a fault condition within 100ns to 200ns, after which the top MOSFET is turned off. The PGOOD filter will delay the signal to the open-drain NMOS transistor connected to the PGOOD pin, however, preventing OV (and UV) transients of less than about 130s from forcing a system reset. Phase-Locked Loop and Frequency Synchronization The LTC3811 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/SYNC pin. The turn-on phase of controller 2's top MOSFET is controlled by the voltage on the PHASEMODE pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLL/LPF pin. The relationship between the voltage on the PLL/LPF pin and operating frequency, when there is a clock signal applied
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VX (MASTER) OUTPUT VOLTAGE
VOUT (SLAVE)
TIME
3811 F19a
(19a) Coincident Tracking
VX (MASTER) OUTPUT VOLTAGE
VOUT (SLAVE)
TIME
3811 F19b
(19b) Ratiometric Tracking Figure 19. Two different Modes of Output Votlage Tracking
Vx VOUT RB RA RTRACKB SS/TRACK RTRACKA 2.5A
3811 F20
LTC3811 VFB
Figure 20. Using the SS/TRACK Pin for Tracking
32
LTC3811 APPLICATIONS INFORMATION
to MODE/SYNC, is shown in Figure 21 and specified in the Electrical Characteristics table. Note that the LTC3811 can only be synchronized to an external clock whose frequency is within range of the LTC3811's internal VCO, which is nominally 125kHz to 1.1MHz. This is guaranteed to be between 175kHz and 900kHz. A simplified block diagram is shown in Figure 22. If the external clock frequency is greater than the internal oscillator's frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLL/LPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLL/LPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLL/LPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01F .
1200 1100 1000 900 FREQUENCY (kHz) 800 700 600 500 400 300 200 100 0 0 0.5 1.5 2 1 PLL/LPF PIN VOLTAGE (V) 2.5
3811 G36
2.4V RLP CLP MODE/ SYNC EXTERNAL OSCILLATOR PLL/LPF DIGITAL PHASE/ FREQUENCY DETECTOR
OSCILLATOR
3811 F22
Figure 22. Phase-Locked Loop Block Diagram
Typically, the external clock (on MODE/SYNC pin) input high threshold is 1.1V, while the input low threshold is 1.0V. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3811 circuits: 1) IC VIN current, 2) DRVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, and the second is the MOSFET driver and control currents. 2. DRVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ
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Figure 21. Relationship Between Oscillator Frequency and Voltage at the PLL/LPF Pin When Synchronizing to an External Clock
33
LTC3811 APPLICATIONS INFORMATION
moves from DRVCC to ground. The resulting dQ/dt is a current out of DRVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying DRVCC and INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V input to 2.5V output application, 40mA of DRVCC current results in approximately 5mA of VIN current. This reduces the mid-current efficiency loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 5m, RL = 1m, RSENSE = 1.5m and RESR = 4m (sum of both input and output capacitance losses), then the total resistance is 16m. This results in losses ranging from 5.6% to 8.4% as the output current increases from 10A to 15A for a 2.5V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: * RDR * CMILLER 2 Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to Translation Loss = (VIN)
2 IMAX
10% efficiency degradation in portable systems. It is very important to include these "system" level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 20m to 50m of ESR. The LTC3811 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 1% total additional loss. Feedback Loop Compensation The LTC3811 incorporates a peak current mode control topology. Peak current mode control provides excellent line and load transient response, and inherently provides the best possible phase-to-phase current sharing in multiphase applications. The LTC3811 incorporates a true operational error amplifier in the feedback loop, enabling the user the flexibility to place poles and zeros at well defined frequencies in the transfer function, thereby optimizing the loop's AC response. The control-to-output transfer function has a pole at the origin in order to provide DC regulation, and a pole due to the load resistance and capacitance at: fP(LOAD) = 1 2 * RL * CL
The output decoupling capacitor ESR contributes a zero to the transfer function at: fZ(ESR) = 1 2 * ESR * CL
The transfer function also has a mathematical double pole at half the switching frequency due to the sampling nature of current mode control, although the pole-splitting behavior of the LTC3811's internal slope compensation reduces the phase shift for frequencies below fSW/2. For most systems, the simple 2-pole, single-zero response of a Type-II compensation network (shown in Figure 23)
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LTC3811 APPLICATIONS INFORMATION
will provide adequate phase margin at the unity-gain frequency of the loop. In a Type-II compensation scheme, the zero is typically placed below the target unity-gain frequency, depending upon the desired settling time of the converter, and the pole is placed no higher than half the switching frequency in order to attenuate the switching frequency from the loop. The gain between the zero and pole is typically adjusted until the desired phase margin is achieved. In general, the output capacitor is chosen based on cost and size considerations, given a certain error budget due to output ripple voltage and load transient response. Oftentimes, multiple capacitor types (such as ceramic and special polymer) are connected in parallel in order
C1 VOUT R2 C2 R4 R2 EA C3 R3
to achieve a good combination of bulk capacitance and low ESR. In general, the output capacitor is not normally chosen to optimize the bode response. Due to their small case size and low ESR, ceramic output capacitors are well suited to very low voltage, high current applications. Their low ESR and relatively high RMS current capability make them a good choice for today's demanding processor-based loads. A fully ceramic output stage, however, will result in very low ESR, pushing the ESR zero frequency relatively close to the unity-gain frequency of the loop. In this case a Type-III compensation network using 3 poles and 2 zeros may be necessary (see Figure 24). For particularly demanding applications requirements, please consult Linear Technology's Applications department.
VOUT C1 C2
R3
R1 0.6V
R1 0.6V
f P1 = f P2 =
1 2 * R2 (C1+ C2) 1 C1* C2 2 * R3 C1+ C2 1 2 * R3 * C2
fP1 = fP2 =
1 2 * R2 (C1+ C2) 1 C1* C2 2 * R3 C1+ C2 1 2 * R4 * C3
fZ =
fP3 =
GAIN (dB)
30 20 10 -20dB DECADE
fZ
fP2 GAIN (dB) R3 R1 f
30 20 10
fZ1
fZ2
AV = 20 log *
-20dB/DECADE
-20dB DECADE
f 90 PHASE (DEG) 45 0 -45 -90
3811 F24
PHASE (DEG)
-45
-90
3811 F23
Figure 23. Type-II Compensation Network and Frequency Response
Figure 24. Type-III Compensation Network and Frequency Response
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+
f Z1 = f Z2 = 1 2 * R3 * C2 1 2 * (R2 + R4) * C3 fP2 fP3 -20dB/DECADE f f
-
EA
+
-
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LTC3811 APPLICATIONS INFORMATION
Measuring the Loop's Transient Response Once the compensation components have been chosen, the AC performance of the power supply should be verified in the lab. The two most common ways of checking the AC response of the circuit are with load and line steps, and by measuring the loop gain using a network analyzer or Venable measurement system. Both of these measurement techniques should be performed on the final design to ensure adequate correlation between the two, and to identify and correct potential regions of marginal stability. These measurements should be performed over all of the load, line, temperature and components tolerance variations the system will experience in a practical application. Figure 25 illustrates a typical load step response for the LTC3811. When a positive load step occurs, the output voltage immediately drops by ILOAD * ESR, where ESR is the equivalent series resistance of the output capacitor. The increased load current then begins to discharge the output capacitor, generating a feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state regulated value. During this recovery time VOUT can be monitored for excessive overshoot or ringing which would indicate a stability problem. Assuming a second order system, the phase margin and/or damping factor can be estimated using the percentage overshoot seen at the output. An output current pulse of 20% to 100% of full load having a rise time of 0.1s to 1s will produce an output voltage waveform that will give an indication of the loop stability without having to break the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator or gate driver is a practical way to produce a realistic load step condition. Voltage Positioning for Single Output, Multiphase Applications The output voltage load line can be programmed with the LTC3811 using one external resistor, allowing the user to reduce the total output capacitance required for a given error budget. The inductor current information is sensed using the SENSE+ and SENSE- inputs for both channels and fed into a transconductance amplifier with two input stages, as shown in Figure 26. The output current of the transconductance amplifier, along with one external resistor (RAVP), allows the user to inject a load-current-related error signal into the voltage feedback loop. Please note that because the gm amplifier mixes the signals from both channels, voltage positioning is only possible for multiphase, single output applications; dual output applications with voltage positioning are not possible. The internal mixing of the current sense signals within the voltage positioning amplifier, combined with the fact that the gm amplifier output signal is a current, allows the user to connect the CSOUT pins of several LTC3811 chips together in multiphase applications. The transconductance (gm) of the voltage positioning amplifier is 2.5mS/phase, and the load slope is: R R2 VOUT = 0.6 * 1+ - IOUT * SENSE * 5m * R AVP n R1
VOUT 50mV/DIV AC COUPLED
where n is the number of phases. The input common mode range of the voltage position gm amplifier is 0.6V to 3.5V, comfortably allowing output voltages up to 3.3V. In addition, the output voltage range of the gm amplifier for linear operation is limited to voltages above 0.6V, due to the headroom requirements of the NMOS sink transistors in the output stage. And finally, the maximum differential input voltage for linear operation is 100mV.
IL 5A/DIV
VIN = 12V 20s/DIV VOUT = 1.5V ILOAD = 0.5A TO 8A
3811 G02
Figure 25. Load Step Response for the LTC3811 Circuit in Figure 33
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LTC3811 APPLICATIONS INFORMATION
L1 L2 SENSE1+ SENSE2+ RS1 RS2 SENSE1- SENSE2- CSOUT VOUT 50mV/DIV AC COUPLED
+ gm -
IL1 5A/DIV IL2 5A/DIV VIN = 12V 50s/DIV VOUT = 1.5V (2-PHASE) ILOAD = 0A TO 15A
3811 G03
CSAMP
RAVP COUT
DIFFIN+ 80k
80k
SGND
Figure 27. Load Step Response for the Circuit in Figure 30
DIFFIN- 80k DIFFOUT COMP C2 R2 R3 C1 FB 0.6V
+ -
80k DIFFAMP
To program 500kHz operation, float the PLL/LPF pin. The inductor value in this design is chosen assuming 50% ripple current. The highest ripple current occurs at maximum input voltage. L= VOUT f * IL V * 1- OUT VIN(MAX)
+ -
EA
3811 F26
R1 SGND
Figure 26. Simplified LTC3811 Voltage Positionig Block Diagram
Figure 27 illustrates the load step response for the circuit in Figure 30, with voltage positioning. A Design Example As a design example consider one channel of a 2-phase single output supply. Assume VIN = 4.5V to 14V, VOUT = 1.5V, IMAX = 30A(15A per phase) and f = 500kHz. In order to achieve the best output accuracy, 1% resistors (or better) should be used in the divider that programs the output voltage. Choosing 600A for the divider current, R2 = 1.5k and R1 = 1k. The nominal output voltage will therefore be 1.50V. For the input and output conditions given above, the steady state minimum on-time for this application at VIN = 14V will be approximately: tON(MIN) = VOUT VIN(MAX ) * f = 1.5V = 214ns 14V * 500kHz
1.5V 1.5V * 1- = 0.36H 500kHz * 0.5 * 15A 14V A 0.4H inductor will result in 6.7A of ripple current, or 45%. Assuming a value for the current limit value 30% greater than the maximum load current, then IMAX = 1.3 * 15A = 19.5A. The peak inductor current will be the maximum DC value plus one half the ripple current, or: = IL(PK ) = 19.5A + 1 * 6.7 A = 22.9 A 2
This represents the minimum saturation current rating for the inductor. For this application, a Vitec 59P9875 inductor was chosen. This inductor has a room temp saturation current rating of 23A and a DCR of 0.32m. To maintain good cycle-by-cycle control of the inductor current and still have good efficiency, a 1.5m, 1W sense resistor from Panasonic (ERJ-M1WTJ1M5U) connected in series with the inductor is used for current sensing. With a maximum peak inductor current of 22.9A, the peak sense voltage will be: VSENSE(PK) = 22.9A * 0.0015 = 34.4mV
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LTC3811 APPLICATIONS INFORMATION
The maximum power dissipation in the sense resistor will be: PR(SENSE) = 22.9A2 * 0.0015 = 0.79W To ensure that the maximum current can be delivered over all of the power component and IC tolerances, the maximum sense voltage for the LTC3811 is chosen to be 50mV. This is programmed by connecting the RNG pin to INTVCC. Due to the use of a 400nH inductor and 500kHz operation, the magnitude of the inductive voltage drop across the sense resistor should be calculated and compared to the maximum sense voltage (50mV). First calculate the nominal switch on-time: tON = VOUT 1.5V = = 250ns VIN * f 12V * 500kHz The power MOSFETs chosen for this application are the Renesas RJK0305DPB (top) and RJK0301DPB (bottom). The upper MOSFET, which is optimized for low switching losses, has a typical RDS(ON) of 10m at VGS = 4.5V, a total gate charge of 8nC, and a minimum BVDSS of 30V. The bottom MOSFET, which is zero-voltage switched and is optimized for low on-resistance, has a typical RDS(ON) of 3m at VGS = 4.5V, a total gate charge of 32nC, and a minimum BVDSS of 20V. From the datasheet of the RJK0305DPB upper MOSFET, the Miller capacitance is calculated to be: CMILLER = QG 2nC = = 167pF VDS 12V
Assuming a top MOSFET junction temperature of 75C, = 0.25 and the power dissipated in this MOSFET is:
PMAIN = VOUT I * IMAX 2 * RDS(ON) * (1+ ) + VIN 2 * MAX T VIN 2 1 1 * RDR * CMILLER * + *f VINTVCC - VTH(MIN) VTH(MIN) PMAIN = 1.5V 15A * 15A 2 * 0.01* (1+ 0.25) + 12V 2 * 12V 2 1 1 * 2 * 167pF * + * 500kHz 6V - 1V 1V PMAIN = 0.351W + 0.216W = 0.567W
The inductor IL/dt is therefore: IL 6.7A 26.8A = = dt 250ns s The Panasonic sense resistor has a typical parasitic series inductance (ESL) of 0.5nH, meaning that the inductive voltage drop across the resistor is: VL(SENSE) = ESL * IL 26.8A = 0.5nH * = 13.4mV dt s
The ESL/R time constant for the sense resistor is therefore: = ESL RSENSE = 333ns
For the synchronous MOSFET the power dissipation is: PSYNC = PMAIN = VIN - VOUT * IMAX 2 * RDS(ON) * (1+ ) VIN 12V - 1.5V * 15A 2 * 0.003 * (1+ 0.25) 12V
The sense pins need an RC filter with the same time constant in order for the waveform at the SENSE+ and SENSE- pin to accurately represent the inductor current. Choosing a value of 1000pF for the filter capacitor, the total resistance should therefore be 333. Split between the SENSE+ and SENSE- pins, each resistor should be 165. These components should be placed adjacent to the SENSE+ and SENSE- pins on the LTC3811, and the PCB traces from the 165 filter resistors should be minimum width and run parallel to each other all the way to the sense resistor location on the board.
= 0.738W To determine the RMS current rating of the input capacitor, we need to first determine the minimum and maximum duty cycle. For an output voltage of 1.5V and an input range of 4.5V to 14V, the duty cycle range is 12.5% to 33.3%. We then use Figure 17 to determine the percentage of
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LTC3811 APPLICATIONS INFORMATION
the maximum load current that represents the minimum RMS current rating of the input capacitor. The worst-case condition occurs when only one output is operational. The output with the highest (VOUT)(IOUT) product should be used to determine the minimum RMS current rating of the input capacitor. From Figure 17 we can see that the worst case condition for this output occurs at the maximum duty cycle of 33.3%, and that the minimum RMS current rating of the input capacitor needs to exceed 7A (47% of 15A). The ceramic output capacitors chosen have an effective ESR of 5m and a bulk capacitance of 660F The peak. to-peak output ripple for this configuration is: 1 VOUT = IL * ESR + 8 * n * f * COUT 1 = 6.7A * 0.005 + 8 * 2 * 500kHz * 660F VOUT = 33.5mV + 1.3mV = 34.8mV This represents a ripple voltage of 2.3%. As can be seen from the calculation, the biggest portion of the output ripple comes from the ESR of the capacitor. This is why low ESR ceramic capacitors are so important in low voltage, high current applications. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter: 1. The connection between the SGND pin on the LTC3811 and all of the small-signal components surrounding the IC should be isolated from the power ground and PGND pin, and should be Kelvin-connected to the main ground node near the bottom terminal of the output capacitors. 2. Place the small-signal components away from high frequency switching nodes on the board. The pinout of the LTC3811 was carefully designed in order to make component placement as easy and noise free as possible. All of the power components can be placed on one side of the IC, away from all of the small-signal components. 3. The bottom terminals of the input and output capacitors should be placed as close as possible to one another, with the small-signal ground connection in between them. This component arrangement will reduce differential mode noise due to the two high di/dt loops in the power circuit. 4. If the output capacitor is located far away from the IC and the remote sense differential amplifier is being used to level-shift the output voltage back to the local IC ground, the small-signal ground around the LTC3811 should be Kelvin-connected to the main ground node near the bottom terminal of the input capacitor. 5. The PGND pin should be connected to the sources of the bottom MOSFETs using a wide, short trace on the top layer of the board. The MOSFETs should also be placed on the top layer of the board. The exposed area on the bottom of the QFN package is internally connected to the PGND node of the IC. 6. Place the INTVCC analog supply decoupling capacitor and resistor right next to the INTVCC and SGND pins on the same layer as the IC. A low ESR 0.1F to 1F ceramic capacitor should be used. 7. Place the DRVCC gate driver supply decoupling capacitor right next the DRVCC and PGND pins, on the same layer as the IC. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR (X5R or better) 4.7F to 10F ceramic capacitor should be used. 8. The floating gate driver supply decoupling capacitor should be located right next the BOOST and SW pins, on the same layer as the IC. This capacitor carries high di/dt currents to drive the upper power MOSFETs. A low ESR (X5R or better) ceramic capacitor at least 100 times the total input capacitance of the upper power MOSFETs for that channel should be used. 9. The resistor divider connected to the FB pin to program the output voltage should be located as near as possible to the IC, with the bottom resistor connecting to the isolated signal ground node near the SGND pin. The PCB trace connecting the top resistor to the upper terminal of the output capacitor should avoid any high
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LTC3811 APPLICATIONS INFORMATION
frequency switching nodes in the circuit and should ideally be shielded (both laterally and vertically) by ground planes. 10. If the differential remote sense amplifier is being used, the PCB traces connecting DIFF/IN+ and DIFF/IN- to the output capacitor should avoid any high frequency switching nodes in the circuit and should ideally be shielded (both laterally and vertically) by ground planes. In addition, the DIFF/IN+ and DIFF/IN- PCB traces should be routed parallel to one another with minimum spacing in between. Due to the 160k input impedance of these pins, it is critical that these traces avoid any high frequency switching nodes in the circuit. 11. The high di/dt loops formed by the input capacitor and the power MOSFETs should be kept as small as possible to avoid EMI and differential mode switching noise. The upper power MOSFETs should be located close to one another and as close as possible to the positive terminal of the input decoupling capacitor. Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 12. The bottom MOSFETs sources should also be located close to one another and as close as possible to the negative terminal of the input capacitor. Since the inductor can be modeled as a current source, its placement on the board is less critical than the high di/dt components. 13. The switch node area should be kept small, with the upper power MOSFET sources and lower power MOSFET drains in close proximity. 14. The filter capacitor between the SENSE+ and SENSE- pins, as well as the filter resistors, should be located as close as possible to the IC. In addition, the connections between the SENSE+ and SENSE- filter resistors and the sense resistor should be routed parallel to one another with minimum spacing in between. These traces should avoid any high frequency switching nodes in the circuit. 15. Keep the switch nodes (SW1, SW2), the top gate nodes (TG1, TG2) and the boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes,
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especially from the opposite channel's voltage- and current-sensing feedback signals. The SW, TG and BOOST nodes can have slew rates in excess of 1V/ns relative to ground and should therefore be kept on the "output side" of the LTC3811. 16. Check the stress on the power MOSFETs by independently measuring the drain-to-source voltages directly across the devices terminals. Beware of inductive ringing that could exceed the maximum voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET. 17. When synchronizing the LTC3811 to an external clock, use a low impedance source such as a logic gate to drive the MODE/SYNC pin and keep the lead as short as possible. 18. Minimize the capacitive load on the CLKOUT pin to minimize excess phase shift. Buffer the CLKOUT signal with an emitter follower if necessary. The diagram in Figure 28 illustrates all the branch currents in a 2-phase single output switching regulator. After studying the waveforms it is clear why it is critical to reduce the area of the high dV/dt nodes as much as possible. High electric and magnetic fields will radiate from these "loops," just as a radio station broadcasts a signal. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the "noise" generated by the switching regulator. The ground terminations of the synchronous MOSFETs and Schottky optional diodes should return to the bottom plate of the input capacitor with a short, isolated PC trace since very high di/dt currents are present. A separate, isolated path from the negative terminals of the input and output capacitors should be used to connect the IC signal ground pin (SGND). This technique keeps inherent signals generated by the high di/dt current pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator.
40
LTC3811 APPLICATIONS INFORMATION
PC Board Layout Debugging Start with one controller on at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter.
SW1
L1
RSENSE1
D1
VIN RIN CIN
VOUT COUT RL
+
+
SW2
L2
RSENSE2
BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH.
D2
3811 F28
Figure 28. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
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41
LTC3811 APPLICATIONS INFORMATION
Reduce VIN from its nominal level to verify operation of the regulator at low VIN. Check the operation of the under-voltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor--don't worry, the regulator will still maintain control of the output voltage.
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42
LTC3811 TYPICAL APPLICATIONS
1 0.1F BAT54 RJK0305DPB 0.1F EXTVCC VIN INTVCC DRVCC TG1 BOOST1 SW1 RJK0301DPB BG1 CLKOUT 1.21k PLL/LPF MODE/SYNC PHASMODE 0.4H 0.5m 680nF 1.21k LTC3811 SENSE1+ SENSE1- RNG2 RNG1 VOUT1 2V 15A RUN2 11.8k 1% 33pF 330F x2 47F X5R 4.99k 1% 100pF RUN1 FB1 COMP1 56k DIFF/OUT FB2 COMP2 100pF 56k 4.99k 1% SENSE2+ SENSE2- DIFF/IN+ DIFF/IN- 7.5k 1% 33pF 47F X5R 1.21k TG2 BOOST2 SW2 BG2 PGND PGOOD1 PGOOD2 CS/OUT 100k 680nF 0.4H 0.5m 100k INTVCC 1.21k RJK0301DPB BAT54 10F X5R RJK0305DPB 47F X5R 330F 16V VIN 4.5V TO 14.5
0.1F
VOUT2 1.5V 15A
SS/TRACK1 SGND SS/TRACK2 5nF
330F x2
3811 F29
2.43k
1.21k
Figure 29. High Efficiency Core-I/O Power Supply with Differential Remote Sensing and Tracking
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43
LTC3811 TYPICAL APPLICATIONS
1F AUX 5V GATE DRIVE SUPPLY 1.0 BAT54 0.33F BAT54 10F X5R RJK0305DPB 0.4H RJK0301DPB 0.0015 100F X5R x4 VIN 12V
100k TO SUPPLY MONITOR 5nF
EXTVCC VIN INTVCC DRVCC BOOST1 PGOOD1 PGOOD2 SS/TRACK1 SS/TRACK2 RNG1 RNG2 MODE/SYNC CLKOUT PLL/LPF PHASEMODE SGND RUN1 RUN2 SENSE2+ SENSE2- LTC3811 TG1 SW1 BG1 PGND SENSE1+ SENSE1- BOOST2 TG2 SW2 BG2
50 2200pF 50 0.33F RJK0305DPB 0.4H RJK0301DPB 50 2200pF 50 500 100F X5R 330F x6 0.0015 VOUT 1V 30A
3.32k 1%
INTVCC 33pF
FB2 FB1 COMP1 COMP2
CSOUT DIFF/IN+ DIFF/IN- DIFF/OUT
4.99k 1%
100pF
285k
3811 F30
100pF
Figure 30. 2-Phase, 12V Input, 1V/30A Output ASIC Supply with Voltage Positioning
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44
LTC3811 TYPICAL APPLICATIONS
1F AUX 5V GATE DRIVE SUPPLY 1.0 BAT54 0.33F BAT54 10F X5R RJK0305DPB 0.4H RJK0301DPB 50 2200pF 50 0.33F RJK0305DPB 0.4H RJK0301DPB 50 2200pF 50 33pF 4.99k 1% 100pF 285k FB1 COMP1 COMP2 SGND DIFF/IN+ DIFF/IN- DIFF/OUT 200F X5R 2000F 0.0015 VOUT1 1.5V 45A 0.0015 47F X5R VIN 12V 470F 100k TO SUPPLY MONITOR 5nF
EXTVCC VIN INTVCC DRVCC PGOOD1 BOOST1 PGOOD2 SS/TRACK1 SS/TRACK2 RNG1 LTC3811 RNG2 MODE/SYNC TG1 SW1 BG1 PGND SENSE1+ SENSE1
-
OUTPUT 1 ON/OFF CONTROL
PHASEMODE FB2 PLL/LPF CLKOUT RUN1 RUN2 7.5k 1%
BOOST2 TG2 SW2 BG2 CSOUT SENSE2+ SENSE2-
100pF
1F
AUX 5V GATE DRIVE SUPPLY
1.0 BAT54 0.33F BAT54 10F X5R
22F X5R
100k TO SUPPLY MONITOR
EXTVCC VIN INTVCC DRVCC PGOOD2 PGOOD1 RNG1 RNG2 FB1 LTC3811 BOOST1 TG1 SW1 BG1 PGND SENSE1+ SENSE1- BOOST2 TG2 SW2 BG2 CSOUT SENSE2+ SENSE2-
RJK0305DPB 0.4H RJK0301DPB 0.0015
50 2200pF 50 0.1F RJK0305DPB 0.4H RJK0301DPB 100F 50 2200pF 50 22F X5R 0.0015 VOUT2 3.3V 5A
5nF
PHASEMODE SS/TRACK2 SS/TRACK1
10k
10nF
CLKOUT PLL/LPF MODE/SYNC RUN1 COMP1 RUN2
22.6k 1% 33pF 100pF 4.99k 28.5k FB2 COMP2 SGND DIFF/OUT DIFF/IN+ DIFF/IN-
Figure 31. 3-Phase, 12V Input, 1.5V/45A Output with a 3.3V/5A Auxiliary Output
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45
LTC3811 PACKAGE DESCRIPTION
UHF Package 38-Lead Plastic QFN (5mm x 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 0.05
5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 3.15 0.05 (2 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.15 0.05 (2 SIDES) 6.10 0.05 (2 SIDES) 7.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (2 SIDES) 0.75 0.05 0.00 - 0.05 3.15 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 37 38 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2
7.00 0.10 (2 SIDES)
5.15 0.10 (2 SIDES)
0.40 0.10 0.200 REF 0.25 0.05 0.75 0.05 0.200 REF 0.00 - 0.05 0.50 BSC R = 0.115 TYP
(UH) QFN 0205
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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46
LTC3811 PACKAGE DESCRIPTION
G Package 36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 - 13.10* (.492 - .516) 1.25 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 - 8.2
5.3 - 5.7 7.40 - 8 (.291 - .
0.42 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 - 5.60** (.197 - .221)
0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) MAX
0 - 8
0.09 - 0.25 (.0035 - .010)
0.55 - 0.95 (.022 - .037)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
0.22 - 0.38 (.009 - .015) TYP
0.05 (.002) MIN
G36 SSOP 0204
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
47
LTC3811 RELATED PARTS
PART NUMBER LTC1628/LTC1628-PG/ LTC1628-SYNC LTC1735 LTC1778/LTC1778-1 LTC3708 LTC3727/LTC3727A-1 LTC3728 LTC3729 LTC3731 LTC3773 LTC3826/ LTC3826-1 LTC3827/LTC3827-1 LTC3828 LTC3835/LTC3835-1 LT3845 LTC3850 DESCRIPTION 2-Phase, Dual Output Synchronous Step-Down DC/DC Controller High Efficiency Synchronous Step-Down Switching Regulator No RSENSETM Current Mode Synchronous Step-Down Controllers Dual, 2-Phase, DC/DC Controller with Output Tracking 2-Phase Dual Synchronous Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Controller 20A to 200A, 550kHz PolyPhase Synchronous Controller 3- to 12-Phase Step-Down Synchronous Controller Triple Output DC/DC Synchronous Controller Ultralow IQ, Dual Output Synchronous Step-Down DC/DC Controller Dual, Selectable 140kHz to 650kHz 2-Phase, Synchronous Step-Down Controller COMMENTS Reduces CIN and COUT, Power Good Output Signal, Synchronizable, 3.5V VIN 36V, IOUT Up to 20A, 0.8V VOUT 5V Output Fault Protection, 16-Pin SSOP Package Up to 97% Efficiency, 4V VIN 36V, 0.8V VOUT (0.9)(VIN), IOUT Up to 20A Current Mode, No RSENSE, Up/Down Tracking, Synchronizable 0.8V VOUT 14V; 4V VIN 36V Dual 180 Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle, 5mm x 5mm QFN and SSOP-28 Packages Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components, VIN Up to 36V 60A to 240A Output Current, 0.6V VOUT 6V, 4.5V VIN 32V 3-Phase Step-Down DC/DC Controller, 3.3V VIN 36V, Fixed Frequency 160kHz to 700kHz 50A IQ, 0.8V VOUT 10V, 4V VIN 36V Low IQ, VIN from 4V to 36V, VOUT from 0.8V to 10V, 5mm x 5mm QFN32
Dual, 2-Phase Synchronous Step-Down Controller with Up to Six Phases, 0.8V VOUT 7V, 4.5V VIN 28V Tracking Low IQ Synchronous Step-Down Controller Low IQ, High Voltage Single Output Synchronous Step-Down DC/DC Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Controller Single Channel LTC3827/LTC3827-1 1.23V VOUT 36V, 4V VIN 60V, 120A IQ Dual 180 Phased Controllers, VIN 4V to 24V, 97% Duty Cycle, 4mm x 4mm QFN-28, SSOP-28 Packages
No RSENSE is a trademark of Linear Technology Corporation.
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48 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0807 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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